CDCM7005

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High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO

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Product details

Parameters

Function Single-loop PLL Number of outputs 5 Number of Inputs 2 Output frequency (Min) (MHz) 0 Output frequency (Max) (MHz) 1500 Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Output type LVCMOS, LVPECL Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 3.6 Features Programmable Delay Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

BGA (ZVA) 64 64 mm² 8 x 8 VQFN (RGZ) 48 49 mm² 7.0 x 7.0 open-in-new Find other Clock jitter cleaners & synchronizers

Features

  • High Performance LVPECL and LVCMOS PLL Clock Synchronizer
  • Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies up to 200 MHz
  • VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
  • VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
  • Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output Individually
  • Efficient Jitter Cleaning From Low PLL Loop Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 µA to 3 mA
  • Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs
  • Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
  • Frequency Hold-Over Mode Improves Fail-Safe Operation
  • Power-up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C

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Description

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O

VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 14
Type Title Date
* Datasheet CDCM7005 3.3-V High Performance Clock Synchronizer and Jitter Cleaner datasheet (Rev. G) Aug. 16, 2017
* Radiation & reliability report CDCM7005MHFG-V Radiation Test Report Nov. 12, 2014
Selection guide TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
User guide TSW3070EVM: Amplifier Interface to Current Sink DAC - (Rev. A) May 23, 2016
Technical articles QAM modulation levels rising: 1024 QAM and beyond Feb. 26, 2014
User guide GC5325 System Evaluation Kit (Rev. F) Apr. 20, 2011
Application note TLK313x/CDCM7005 Multi-hop Performance Nov. 01, 2009
User guide TSW4100EVM User's Guide (Rev. A) Sep. 16, 2008
More literature TSW3003: RF Transmit Signal Chain Demonstration Kit Bulletin Sep. 28, 2006
User guide CDCM7005 (BGA Package) Evaluation Module Manual (Rev. A) Dec. 19, 2005
User guide CDCM7005 (QFN Package) EVM Users Guide (Rev. A) Dec. 19, 2005
Application note Phase Noise/Phase Jitter Performance of CDCM7005 Jul. 26, 2005
User guide CDCM7005 (QFN Package) EVM Manual Jul. 14, 2005
User guide CDCM7005 (BGA Package) Evaluation Module Manual Jun. 27, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The ADS5474EVM is a circuit board which allows the designer to run an evaluation of Texas Instruments ADS5474 device, a 14-bit 400 MSPS ADC. With the supplied Logic analyzer breakout board, the ADC LVDS output can be directly captured using either an Agilent E5405A or Tektronix P6980 touchless (...)

Features
  • Transformer coupled analog input path
  • Texas Instrument’s THS9001 analog input path
  • LVDS capture ability
EVALUATION BOARD Download
Description

The ADS5483EVM is a circuit board which allows the designer to run an evaluation of Texas Instruments’ ADS5483 device, a 16-bit 135 MSPS ADC with DDR LVDS outputs. With the supplied logic analyzer breakout board, the ADC LVDS output can be directly captured using either an Agilent E5405A or (...)

Features
  • Transformer coupled analog input path
  • CDCE72010 Jitter Clock Synchronizer and Jitter Cleaner clocking circuit
  • DDR LVDS output and capture ability
EVALUATION BOARD Download
199
Description

The CDC7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.

The PLL loop bandwidth and damping factor can be adjusted to meet (...)

Features
  • Operates up to 800 MHz
  • Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
  • Can be used as a simple 1:5 LVPECL buffer with output dividing options
  • Differential outputs programmable by serial peripheral interface (SPI)
EVALUATION BOARD Download
199
Description

The CDCE72010EVM is the evaluation module for CDCE72010 - 10 outputs low jitter clock synchornizer. CDCE72010 can be programmed through the SPI interface using the evaluation module (EVM)programming GUI. The evaluation module (EVM) is designed to demonstrate the electrical performance of the (...)

Features
  • Easy-to-use evaluation board to generate low-phase noise clocks up to 1.5 GHz
  • Easy device programming via host-powered USB port
  • Fast configuration through provided graphical user interface (GUI) software interface
  • Total board power provided either through USB port or separate 3.3 V and ground (...)
EVALUATION BOARD Download
199
Description

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.

The PLL loop bandwidth and damping factor can be adjusted to meet (...)

Features
  • Output frequency up to 1500 MHz
  • Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
  • Can be used as a simple 1:5 LVPECL buffer with output dividing options
  • Differential outputs programmable by serial peripheral interface (SPI)
EVALUATION BOARD Download
199
Description

TheCDCM7005QFN-EVM is an evaluation module designed to aid in evaluating the performance of the CDCM7005, which is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates (...)

Features
  • Output frequency up to 1500 MHz
  • Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
  • Can be used as a simple 1:5 LVPECL buffer with output dividing options
  • Differential outputs programmable by serial peripheral interface (SPI)
EVALUATION BOARD Download
499
Description

The DAC5688EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x/8x interpolation filters, on-board clock multiplier and PLL, 32-bit NCO and (...)

Features
  • Comprehensive test capability for DAC5688
  • Direct connection to TSW3100 signal generator EVM
  • Has a programmable Low Jitter Clock Synthesizer capable of working with a VCXO or an external clock source
  • Clock synchronization with TSW3100 for signal integrity
  • Software support with a fully featured GUI for (...)

Design tools & simulation

SIMULATION MODEL Download
SCAC060.ZIP (37 KB) - IBIS Model
SIMULATION MODEL Download
SCAC061B.ZIP (43 KB) - IBIS Model
SIMULATION MODEL Download
SCAC062.ZIP (37 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOL Download
CDC7005 and CDCM7005 PLL Loop Bandwidth Calculator
CDC-CDCM7005-CALC This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump (...)
Features

The lab view based tool can:

  • Determine the PFD frequency automatically
  • Calculate loop bandwidth, Phase margin and Jitter peaking
  • Predict the PLL output Phase noise
  • Calculate Phase Jitter (rms)
GERBER FILE Download
SCAC064.ZIP (669 KB)
GERBER FILE Download
SCAC065.ZIP (567 KB)

Reference designs

REFERENCE DESIGNS Download
LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
TIDA-01187 — Time-of-flight (ToF) optical methods for measuring distance with high precision are utilized in a variety of applications, such as laser safety scanners, range finders, drones, and guidance systems. This design details the advantages of a high-speed data-converter-based solution, including target (...)
document-generic Schematic
REFERENCE DESIGNS Download
Wide-Bandwidth and High-Voltage Arbitrary Waveform Generator Front End
TIDA-00075 This design shows how to use an active interface with the current sink output of the DAC5682Z - typical applications for this include front ends for arbitrary waveform generators. The EVM includes the DAC5682Z for digital-to-analog conversion, an OPA695 to demonstrate an active interface (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
BGA (ZVA) 64 View options
VQFN (RGZ) 48 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
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  • Qualification summary
  • Ongoing reliability monitoring

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