Product details

Resolution (Bits) 14 Sample/update rate (MSPS) 9000 Number of DAC channels (#) 2 Interpolation 10x, 12x, 16x, 18x, 20x, 24x, 6x, 8x Output Single-ended Power consumption (Typ) (mW) 3800 Operating temperature range (C) -40 to 85
Resolution (Bits) 14 Sample/update rate (MSPS) 9000 Number of DAC channels (#) 2 Interpolation 10x, 12x, 16x, 18x, 20x, 24x, 6x, 8x Output Single-ended Power consumption (Typ) (mW) 3800 Operating temperature range (C) -40 to 85
FCBGA (AAV) 144 100 mm² 10 x 10
  • 14-Bit Resolution
  • Maximum DAC Sample Rate: 9 GSPS
  • Key Specifications:
    • RF Full-Scale Output Power at 2.1 GHz:
      • DAC38RF80/90/84: 0 dBm
      • DAC38RF83/93/85: 3 dBm (with 2:1 balun)
    • Spectral Performance(on-chip PLL, DIFF):
      • fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
        • WCDMA ACLR: 75 dBc
        • WCDMA alt-ACLR: 77 dBc
      • fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
        • 20 MHz LTE ACLR: 63 dBc
      • fDAC = 9 GSPS, fOUT = 1.8 GHz
        • IMD3 = 70 dBc (–6 dBFS, 10-MHz tone spacing)
        • NSD = –157 dBc/Hz
  • Dual-Band Digital Up-converter per DAC
    • 6, 8, 10, 12, 16, 18, 20 or 24x Interpolation
    • 4 Independent NCOs With 48-Bit Resolution
  • JESD204B Interface, Subclass 1
    • Support for Multichip Synchronization
    • Maximum Lane Rate: 12.5 Gbps
  • Single-Ended Output With Integrated Balun (DAC38RF80/90/84) Covering 700 MHz to 3800 MHz
  • Internal PLL and VCO With Bypass
    • fC(VCO) = 5.9 or 8.9 GHz
  • Power Dissipation: 1.4 to 2.2 W/ch
  • Power Supplies: –1.8 V, 1 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm Pitch, 144-Balls
  • 14-Bit Resolution
  • Maximum DAC Sample Rate: 9 GSPS
  • Key Specifications:
    • RF Full-Scale Output Power at 2.1 GHz:
      • DAC38RF80/90/84: 0 dBm
      • DAC38RF83/93/85: 3 dBm (with 2:1 balun)
    • Spectral Performance(on-chip PLL, DIFF):
      • fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
        • WCDMA ACLR: 75 dBc
        • WCDMA alt-ACLR: 77 dBc
      • fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
        • 20 MHz LTE ACLR: 63 dBc
      • fDAC = 9 GSPS, fOUT = 1.8 GHz
        • IMD3 = 70 dBc (–6 dBFS, 10-MHz tone spacing)
        • NSD = –157 dBc/Hz
  • Dual-Band Digital Up-converter per DAC
    • 6, 8, 10, 12, 16, 18, 20 or 24x Interpolation
    • 4 Independent NCOs With 48-Bit Resolution
  • JESD204B Interface, Subclass 1
    • Support for Multichip Synchronization
    • Maximum Lane Rate: 12.5 Gbps
  • Single-Ended Output With Integrated Balun (DAC38RF80/90/84) Covering 700 MHz to 3800 MHz
  • Internal PLL and VCO With Bypass
    • fC(VCO) = 5.9 or 8.9 GHz
  • Power Dissipation: 1.4 to 2.2 W/ch
  • Power Supplies: –1.8 V, 1 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm Pitch, 144-Balls

The DAC38RFxx is a family of high-performance, dual/single-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.

The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. An optional low-jitter PLL/VCO simplifies the DAC sampling clock generation by allowing use of a lower frequency reference clock.

The DAC38RFxx is a family of high-performance, dual/single-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.

The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. An optional low-jitter PLL/VCO simplifies the DAC sampling clock generation by allowing use of a lower frequency reference clock.

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Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DAC38RF80EVM — DAC38RF80 Dual-Channel, 14-Bit, 9-GSPS, 6x-24x Interpolating, 6 & 9 GHz PLL DAC Evaluation Module

The DAC38RF80EVM is the circuit board for evaluating DAC38RF80/84/90 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate. It is designed to work with the FPGA-based pattern generator card TSW14J56EVM (Rev B and up). The (...)

In stock
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Evaluation board

TSW40RF80EVM — 2T2R RF-Sampling Transceiver w/ Dual 14-Bit 3GSPS ADC/9GSPS DAC Clocking Solution Evaluation Module

The TSW40RF80 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF80 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The (...)

In stock
Limit: 3
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Firmware

Arria10 + DAC38RF82 Design Firmware (Rev. A)

SLAC771A.ZIP (10836 KB)
Firmware

DAC38RF8x KCU105 Firmware (Rev. A)

SLAC779A.ZIP (48623 KB)
GUI for evaluation module (EVM)

DAC38RF8x EVM GUI (Rev. D)

SLAC722D.ZIP (216778 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

DAC38RF80 IBIS Model

SLAM304.ZIP (70 KB) - IBIS Model
Simulation model

DAC38RF8x IBIS-AMI Model (Rev. A)

SLAM343A.ZIP (24658 KB) - IBIS-AMI Model
Schematic

DAC38RF8xEVM Design Files

SLAC734.ZIP (10565 KB)
Gerber file

TSW40RF80EVM Design File

SLAC751.ZIP (9967 KB)
Reference designs

TIDA-01215 — Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs

This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x (...)
Reference designs

TIDA-01240 — RF-Sampling S-Band Radar Transmitter Reference Design

Synthesis of waveforms appropriate for an S-band multifunction phased array radar (MPAR) is demonstrated with an RF sampling architecture utilizing the DAC38RF80, a 9GSPS 16-bit digital-to-analog converter (DAC). The RF sampling transmit architecture simplifies the signal chain, bringing the data (...)
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FCBGA (AAV) 144 View options

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