DAC39J82
Dual-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)
DAC39J82
- Resolution: 16-Bit
- Maximum Sample Rate: 2.8GSPS
- Maximum Input Data Rate: 1.4GSPS
- JESD204B Interface
- 8 JESD204B Serial Input Lanes
- 12.5 Gbps Maximum Bit Rate per Lane
- Subclass 1 Multi-DAC synchronization
- On-Chip Very Low Jitter PLL
- Selectable 1x -16x Interpolation
- Independent Complex Mixers with 48-bit NCO/
or ±n×Fs/8 - Wideband Digital Quadrature Modulator Correction
- Sinx/x Correction Filters
- Fractional Sample Group Delay Correction
- Flexible Routing to Four Analog Outputs via Output
Multiplexer - 3/4-Wire Serial Control Bus (SPI)
- Integrated Temperature Sensor
- JTAG Boundary Scan
- Pin-compatible with Quad-channel DAC39J84
- Power Dissipation: 1.1W at 2.8GSPS
- Package: 10x10mm, 144-Ball Flip-Chip BGA
The DAC39J82 is a very low power, 16-bit, dual-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.4 GSPS.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
DAC39J82 provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | DAC39J82 Dual-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface datasheet | PDF | HTML | 26 Jan 2015 |
Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 27 Sep 2017 | ||
EVM User's guide | DAC3XJ8XEVM User's Guide (Rev. B) | 28 Apr 2016 | ||
Application note | System solution for avionics & defense | 23 Sep 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
DAC39J82EVM — DAC39J82 Dual-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter EVM
The DAC39J82EVM is an evaluation module (EVM) designed to evaluate the DAC39J82EVMhigh-speed, JESD204B interface DAC. The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software GUI and USB interface.
The DAC39J82EVM is (...)
TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
TIDA-00996 — Synchronized Multi-Transmitter Reference Design: Method of Time-Aligning Multiple DACs
TIDA-00335 — High Bandwidth, High Frequency Transmitter Reference Design
Package | Pins | Download |
---|---|---|
FCCSP (AAV) | 144 | View options |
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