Product details

Resolution (Bits) 16 Number of DAC channels 2 Interface type JESD204B Sample/update rate (Msps) 2800 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1135 SFDR (dB) 81 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type JESD204B Sample/update rate (Msps) 2800 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1135 SFDR (dB) 81 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
FCCSP (AAV) 144 100 mm² 10 x 10
  • Resolution: 16-Bit
  • Maximum Sample Rate: 2.8GSPS
  • Maximum Input Data Rate: 1.4GSPS
  • JESD204B Interface
    • 8 JESD204B Serial Input Lanes
    • 12.5 Gbps Maximum Bit Rate per Lane
    • Subclass 1 Multi-DAC synchronization
  • On-Chip Very Low Jitter PLL
  • Selectable 1x -16x Interpolation
  • Independent Complex Mixers with 48-bit NCO/
    or ±n×Fs/8
  • Wideband Digital Quadrature Modulator Correction
  • Sinx/x Correction Filters
  • Fractional Sample Group Delay Correction
  • Flexible Routing to Four Analog Outputs via Output
    Multiplexer
  • 3/4-Wire Serial Control Bus (SPI)
  • Integrated Temperature Sensor
  • JTAG Boundary Scan
  • Pin-compatible with Quad-channel DAC39J84
  • Power Dissipation: 1.1W at 2.8GSPS
  • Package: 10x10mm, 144-Ball Flip-Chip BGA
  • Resolution: 16-Bit
  • Maximum Sample Rate: 2.8GSPS
  • Maximum Input Data Rate: 1.4GSPS
  • JESD204B Interface
    • 8 JESD204B Serial Input Lanes
    • 12.5 Gbps Maximum Bit Rate per Lane
    • Subclass 1 Multi-DAC synchronization
  • On-Chip Very Low Jitter PLL
  • Selectable 1x -16x Interpolation
  • Independent Complex Mixers with 48-bit NCO/
    or ±n×Fs/8
  • Wideband Digital Quadrature Modulator Correction
  • Sinx/x Correction Filters
  • Fractional Sample Group Delay Correction
  • Flexible Routing to Four Analog Outputs via Output
    Multiplexer
  • 3/4-Wire Serial Control Bus (SPI)
  • Integrated Temperature Sensor
  • JTAG Boundary Scan
  • Pin-compatible with Quad-channel DAC39J84
  • Power Dissipation: 1.1W at 2.8GSPS
  • Package: 10x10mm, 144-Ball Flip-Chip BGA

The DAC39J82 is a very low power, 16-bit, dual-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.4 GSPS.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

DAC39J82 provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.

The DAC39J82 is a very low power, 16-bit, dual-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.4 GSPS.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

DAC39J82 provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.

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Technical documentation

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Type Title Date
* Data sheet DAC39J82 Dual-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface datasheet PDF | HTML 26 Jan 2015
Application note DAC3xJ8x Device Initialization and SYSREF Configuration 27 Sep 2017
EVM User's guide DAC3XJ8XEVM User's Guide (Rev. B) 28 Apr 2016
Application note System solution for avionics & defense 23 Sep 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DAC39J82EVM — DAC39J82 Dual-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter EVM

 The DAC39J82EVM is an evaluation module (EVM) designed to evaluate the DAC39J82EVMhigh-speed, JESD204B interface DAC. The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software GUI and USB interface.

The DAC39J82EVM is (...)

User guide: PDF
Not available on TI.com
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
GUI for evaluation module (EVM)

SLAC644 DAC3XJ8XEVM Software

Supported products & hardware

Supported products & hardware

Products
High-speed DACs (>10 MSPS)
DAC37J82 Dual-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC) DAC37J84 Quad-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC) DAC38J82 Dual-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC) DAC38J84 Quad-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC) DAC39J82 Dual-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC) DAC39J84 Quad-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)
Hardware development
Evaluation board
DAC37J82EVM DAC37J82 Dual-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating DAC Evaluation Module DAC37J84EVM DAC37J84 Quad-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating DAC Evaluation Module DAC38J82EVM DAC38J82 Dual-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating Digital-to-Analog Converter EVM DAC38J84EVM DAC38J84 Quad-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating DAC Evaluation Module DAC39J82EVM DAC39J82 Dual-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter EVM DAC39J84EVM DAC39J84 Quad-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter EVM
Simulation model

DAC38J84 IBIS Model

SLAM197.ZIP (50 KB) - IBIS Model
Simulation model

DAC38RF8x IBIS-AMI Model (Rev. A)

SLAM343A.ZIP (24658 KB) - IBIS-AMI Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00996 — Synchronized Multi-Transmitter Reference Design: Method of Time-Aligning Multiple DACs

To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00335 — High Bandwidth, High Frequency Transmitter Reference Design

This design illustrates the circuit modifications required to support high bandwidth and  high frequency applications using current source DACs like the  DAC38J84 with the TRF3704 modulator.  The TRF3704 is a 6 GHz modulator capable of supporting wide BB bandwidths.  The (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
FCCSP (AAV) 144 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

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