Product details


Type Retimer Mux Number of channels (#) 16 Input compatibility AC-coupling, CML Speed (Max) (Gbps) 12.5 Operating temperature range (C) -40 to 85 Protocols 10G-SR/LR, 40G-SR4/LR4, Infiniband, CPRI, Interlaken, General purpose open-in-new Find other Ethernet retimers, redrivers & mux-buffers

Package | Pins | Size

FC/CSP (ABB) 196 225 mm² 15 x 15 open-in-new Find other Ethernet retimers, redrivers & mux-buffers


  • Pin-Compatible Family
    • DS150DF1610: 12.5 to 15 G
    • DS125DF1610: 9.8 to 12.5 G
    • DS110DF1610: 8.5 to 11.3 G
  • 4x4 Analog Cross Point Switch for Each Quad
  • Fully Adaptive CTLE
  • Self tuning DFE, with Optional Continuous Adaption
  • Configurable VGA
  • Adjustable Transmit VOD
  • Adjustable 3-tap Transmit FIR Filter
  • On-chip AC Coupling on Receive Inputs
  • Locks to Half/Quarter/Eighth Data Rates for Legacy Support
  • On-chip Eye Monitor(EOM), PRBS Checker, Pattern Generator
  • Supports JTAG Boundary Scan
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection
  • Single 2.5 V ±5% Power Supply
  • SMBus Based Register Configuration
  • Optional EEPROM Configuration
  • 15 mm × 15 mm, 196-pin FCBGA Package
  • Operating Temp Range : –40°C to +85°C

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The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.

Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.

Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.

A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.

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Technical documentation

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Type Title Date
* Data sheet DS125DF1610 9.8 to 12.5 Gbps 16-Channel Retimer datasheet (Rev. B) Jan. 13, 2017
Application note Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications May 15, 2020
User guide DS125DF1610EVM User's Guide (Rev. B) Sep. 20, 2018
Technical article Eye doctor: Reflections and how to deal with them in high-speed systems Sep. 08, 2016
Application note Green box testing: A method for optimizing high-speed serial links Jul. 21, 2016
Application note Understanding EEPROM Programming for 10G to 12.5G Retimers Jan. 13, 2016
Technical article Make signal conditioning easy with WEBENCH® Interface Designer Jan. 27, 2015
Application note Selecting TI SigCon Devices for SFF-8431 SFP+ Applications May 06, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The DS125DF1610EVM allows for easy evaluation of the DS125DF1610.  Users are required to supply power and high speed traffic to the EVM via the SMA connectors. A low cost on board oscillator provides a reference clock for the DS125DF1610’s PPM counter, so external clocking equipment is not required.


  • Programmable via SMBus port
  • Supports 9.8 Gbps to 12.5 Gbps and divide by 2, 4, 8 data rates
  • 4x4 analog cross point switch
  • JTAG port for IEEE 1149.1 and 1149.6
  • EVM support single supply (2.5V or 3.3V)

Design tools & simulation

SNLM143.PDF (25 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

Reference designs

12-Gbps Multi-Channel BERT Board Reference Design
TIDA-00426 — This reference design is a 12-Gbps low-cost bit error tester (BERT) capable of generating and checking up to 8 channels of pseudo-random binary sequences (PRBS). This validated design is a convenient way to generate multi-channels high speed serial bit streams of up to 12-Gbps, and checking incoming (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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FCBGA (ABB) 196 View options

Ordering & quality

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  • Ongoing reliability monitoring

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