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Product details

Parameters

Function Equalizer Protocols LVDS, LVPECL, CML Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 12500 Input signal LVDS, LVPECL, CML Output signal LVDS, LVPECL, CML Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

WSON (NGF) 6 6 mm² 2.2 x 2.5 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • 5 to 12.5 Gbps Operation
  • No Power or Ground Required
  • Equalization Effective Anywhere in Data Path
  • Equalizes CML, LV-PECL, LVDS Signals
  • Symmetric I/O Structures Provide Equal Boost for Bi-directional Operation
  • 7 dB Maximum Boost
  • Code Independent, 8b/10b or Scrambled
  • Supports Both Bi-level and Multi-level Signaling
  • Extends Reach Over Backplanes and Cables
  • Compatible with PCI-Express Gen1 and Gen2
  • Compatible with XAUI
  • Will Operate in Series with Existing Active Equalizer
  • Easy to Handle 6 Pin WSON

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Description

TI’s Power-saver equalizer compensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 5 to 12.5 Gbps. The DS80EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 traces and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear compensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling.

The equalizer is available in a 6 pin leadless WSON package with a space saving 2.2 mm X 2.5 mm footprint. This tiny package provides maximum flexibility in placement and routing of the Power-saver equalizer.

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Technical documentation

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Type Title Date
* Datasheet DS80EP100 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables datasheet (Rev. C) Feb. 19, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
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Description

TI's Power-saver equalizer compensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 5 to 12.5 Gbps.

Features
  • 5 to 12.5 Gbps Operation
  • No Power or Ground Required
  • Equalization effective anywhere in data path
  • Equalizes CML, LV-PECL, LVDS signals
  • Symmetric I/O structures provide equal boost for bi-directional operation
  • 7 dB Maximum Boost
  • Code independent, 8b/10b or Scrambled
  • Supports both bi-level and multi-level (...)

Design tools & simulation

SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
WSON (NGF) 6 View options

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