Packaging information
| Package | Pins SOIC (DW) | 16 |
| Operating temperature range (°C) -40 to 125 |
| Package qty | Carrier 2,000 | LARGE T&R |
Features for the ISO6760L
- ISO6760 with integrated Interlock function
- Designed to support opposite polarity of adjacent channels
- Three sets of paired interlock channels
- Robust isolation barrier:
- High lifetime at 1500 VRMS working voltage
- Up to 5000 VRMS isolation rating
- Up to 10 kV surge capability
- ±130 kV/µs typical CMTI
- Wide supply range: 1.71 V to 1.89 V and 2.25 V to 5.5 V
- Channel output non-inverting (ISO6760L) and inverting (ISO6760LN) options
- 50 Mbps data rate
- 1.71 V to 5.5 V level translation
- Wide temperature range: –40°C to 125°C
- 1.4 mA per channel typical at 1 Mbps
- Robust electromagnetic compatibility (EMC)
- System-level ESD, EFT, and surge immunity
- Low emissions
- Wide-SOIC (DW-16) Package
- Safety-Related Certifications:
- DIN EN IEC 60747-17 (VDE 0884-17)
- UL 1577 component recognition program
- IEC 62368-1, IEC 61010-1, IEC 60601-1 and GB 4943.1 certifications
Description for the ISO6760L
The ISO6760L and ISO6760LN devices are high-performance, six-channel digital isolators with integrated interlock function for applications requiring up to 5000 VRMS isolation ratings per UL 1577. These devices are also certified by VDE, TUV, CSA, and CQC.
The ISO6760L family of devices integrate a series of logic gates to provide hardware interlock functionality for adjacent channels. The interlock feature ensures that each channel, in a channel pairing, will not be enabled at the same time. If both channels in the pairing share the same input logic, the output logic will always be low. The ISO6760L family of devices have all six channels in the same direction and provide high electromagnetic immunity and low emissions at low power consumption, while isolating CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer separated by TI’s double capacitive silicon dioxide (SiO2) insulation barrier.
Used in conjunction with intelligent power modules (IPMs), the interlock feature in these devices help prevent shoot through current between the high side and low side gate driver during turn on and turn off events. Six channels, including three pairings of interlock circuitry, are integrated in a 16-pin SOIC wide-body (DW) package with space savings greater than 50% compared to optocoupler solutions. Through innovative chip design and layout techniques, the electromagnetic compatibility of the ISO6760L devices has been significantly enhanced to ease system-level ESD, EFT, surge, and emissions compliance.