4.5-A, 30-V half bridge gate driver for synchronous/asynchronous drive
Product details
Parameters
Package | Pins | Size
Features
- Adaptive Shoot-through Protection
- 10ns Dead Time
- 8ns Propagation Delay
- 30ns Minimum On-time
- 0.4Ω Pull-down and 0.9Ω Pull-up Drivers
- 4.5A Peak Driving Current
- MOSFET Tolerant Design
- 5µA Quiescent Current
- 30V Maximum Input Voltage in Buck Configuration
- 4V to 6.85V Operating Voltage
- SOIC-8 and WSON Packages
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Description
The LM27222 is a dual N-channel MOSFET driver designed to drive MOSFETs in push-pull configurations as typically used in synchronous buck regulators. The LM27222 takes the PWM output from a controller and provides the proper timing and drive levels to the power stage MOSFETs. Adaptive shoot-through protection prevents damaging and efficiency reducing shoot-through currents, thus ensuring a robust design capable of being used with nearly any MOSFET. The adaptive shoot-through protection circuitry also reduces the dead time down to as low as 10ns, ensuring the highest operating efficiency. The peak sourcing and sinking current for each driver of the LM27222 is about 3A and 4.5Amps respectively with a Vgs of 5V. System performance is also enhanced by keeping propagation delays down to 8ns. Efficiency is once again improved at all load currents by supporting synchronous, non-synchronous, and diode emulation modes through the LEN pin. The minimum output pulse width realized at the output of the MOSFETs is as low as 30ns. This enables high operating frequencies at very high conversion ratios in buck regulator designs. To support low power states in notebook systems, the LM27222 draws only 5µA from the 5V rail when the IN and LEN inputs are low or floating.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | LM27222 High-Speed 4.5A Synchronous MOSFET Driver datasheet (Rev. B) | Mar. 07, 2013 |
Application note | External Gate Resistor Selection Guide (Rev. A) | Feb. 28, 2020 | |
Application note | Understanding Peak IOH and IOL Currents (Rev. A) | Feb. 28, 2020 | |
More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | Oct. 29, 2018 | |
Technical articles | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | Sep. 19, 2018 | |
Technical articles | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | May 30, 2018 | |
Technical articles | Boosting efficiency for your solar inverter designs | May 24, 2018 | |
Technical articles | How to achieve higher system robustness in DC drives, part 1: negative voltage | Apr. 17, 2018 |
Design & development
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Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
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CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 8 | View options |
WSON (NGT) | 8 | View options |
Ordering & quality
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