Product details

Number of input channels 2 Resolution (Bits) 14 Sample rate (Max) (MSPS) 370 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 800 SFDR (Typ) (dB) 88 SNR (Typ) (dB) 71.9 Power consumption (Typ) (mW) 1752 Logic voltage DV/DD (Max) (V) 1.25 Logic voltage DV/DD (Min) (V) 1.15 Analog voltage AVDD (Max) (V) 3.45 Analog voltage AVDD (Min) (V) 1.15 Operating temperature range (C) -40 to 85 Rating Catalog
Number of input channels 2 Resolution (Bits) 14 Sample rate (Max) (MSPS) 370 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 800 SFDR (Typ) (dB) 88 SNR (Typ) (dB) 71.9 Power consumption (Typ) (mW) 1752 Logic voltage DV/DD (Max) (V) 1.25 Logic voltage DV/DD (Min) (V) 1.15 Analog voltage AVDD (Max) (V) 3.45 Analog voltage AVDD (Min) (V) 1.15 Operating temperature range (C) -40 to 85 Rating Catalog
WQFN (RME) 56 64 mm² 8 x 8
  • Conversion Rate: 370 MSPS
  • 1.7 VP-P Input Full Scale Range
  • SNRBoost Noise Shaping with 100 MHz Bandpass Bandwidth
    • Noise Spectral Density: –152.0 dBFS/Hz
    • Programmable Passband Center Frequency
  • Bit-Burst Resolution Switching
    • Resolutions: 9-bit (Low-Res), 14-bit (Hi-Res)
    • Hi-Res Noise Density: –152.7 dBFS/Hz
    • Programmable Burst Configurations
  • Performance
    • Input: 150 MHz, –3 dBFS
      • SNR (SNRBoost): 71.6 dBFS
      • SNR (Bit-Burst): 69.6 dBFS
      • SFDR: 88 dBFS
      • non-HD2/HD3 SPUR: –90 dBFS
  • Power Dissipation: 876 mW/channel
  • Buffered Analog Inputs
  • On-chip Precision Reference Without External Bypassing
  • Input Sampling Clock Divider with Phase Synchronization
    (Divide-by- 1, 2, 4 or 8)
  • JESD204B Subclass 1 Serial Data Interface
    • Lane Rates up to 7.4 Gb/s
    • Configurable as 1- or 2-lanes/channel
  • Fast Over-range Signals
  • 4-wire, 1.2 V, 1.8 V, 2.5V or 3.3V Compatible SPI
  • 56-pin QFN Package, (8 × 8 mm, 0.5mm pin-pitch)
  • Conversion Rate: 370 MSPS
  • 1.7 VP-P Input Full Scale Range
  • SNRBoost Noise Shaping with 100 MHz Bandpass Bandwidth
    • Noise Spectral Density: –152.0 dBFS/Hz
    • Programmable Passband Center Frequency
  • Bit-Burst Resolution Switching
    • Resolutions: 9-bit (Low-Res), 14-bit (Hi-Res)
    • Hi-Res Noise Density: –152.7 dBFS/Hz
    • Programmable Burst Configurations
  • Performance
    • Input: 150 MHz, –3 dBFS
      • SNR (SNRBoost): 71.6 dBFS
      • SNR (Bit-Burst): 69.6 dBFS
      • SFDR: 88 dBFS
      • non-HD2/HD3 SPUR: –90 dBFS
  • Power Dissipation: 876 mW/channel
  • Buffered Analog Inputs
  • On-chip Precision Reference Without External Bypassing
  • Input Sampling Clock Divider with Phase Synchronization
    (Divide-by- 1, 2, 4 or 8)
  • JESD204B Subclass 1 Serial Data Interface
    • Lane Rates up to 7.4 Gb/s
    • Configurable as 1- or 2-lanes/channel
  • Fast Over-range Signals
  • 4-wire, 1.2 V, 1.8 V, 2.5V or 3.3V Compatible SPI
  • 56-pin QFN Package, (8 × 8 mm, 0.5mm pin-pitch)

The LM97937 device is a dual-channel 370 MSPS analog-to-digital converter (ADC) with JESD204B interface operating up to 7.4 Gb/s. SNRBoost technology with bandpass spectral shaping improves the noise density at the intermediate frequency and Bit-Burst technology provides temporary and periodic resolution enhancement. The integrated input buffer reduces charge kick-back noise and eases the system level design of the driving amplifier, anti-aliasing filter and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. The device comes in a 56-pin, 8-mm × 8-mm QFN package.

The LM97937 device is a dual-channel 370 MSPS analog-to-digital converter (ADC) with JESD204B interface operating up to 7.4 Gb/s. SNRBoost technology with bandpass spectral shaping improves the noise density at the intermediate frequency and Bit-Burst technology provides temporary and periodic resolution enhancement. The integrated input buffer reduces charge kick-back noise and eases the system level design of the driving amplifier, anti-aliasing filter and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. The device comes in a 56-pin, 8-mm × 8-mm QFN package.

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Technical documentation

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Type Title Date
* Data sheet LM97937 Dual 370 MSPS Receiver and Feedback IC With SNRBoost, Bit-Burst, JESD20 datasheet (Rev. A) 31 Jan 2014
Technical article Why should you care about the noise immunity of MLVDS drivers and receivers? 26 Jul 2017
Technical article How to minimize filter loss when you drive an ADC 20 Oct 2016
Technical article RF sampling: analog-to-digital converter linearity sets sensitivity 29 Sep 2016
Technical article RF sampling: linearity performance is not so straightforward 30 Aug 2016
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 19 Mar 2015
Application note Equalization Optimization of the ADC16DX370 JESD204B Serial Link 09 Sep 2014
User guide LM97937 User's Guide 09 Dec 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LM97937EVM — LM97937 Dual-Channel 370MSPS Receiver and Feedback IC Evaluation Module

The LM97937EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ LM97937. The LM97937 is a low power, 9-bit, 370-MSPS analog to digital converter (ADC) with a buffered analog input, backend SNRBoost and Bit-Burst signal processing and outputs featuring a (...)

User guide: PDF
Not available on TI.com
GUI for evaluation module (EVM)

LM97937EVM Configuration GUI (Rev. A)

SLAC641A.ZIP (174428 KB)
lock = Requires export approval (1 minute)
Simulation model

LM97937 IBIS Model

SNVM537.ZIP (721 KB) - IBIS Model
Reference designs

TIDA-00360 — 700–2700 MHz Dual-Channel Receiver with 16-Bit ADC and 100 MHz IF Bandwidth Reference Design

The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00353 — Equalization Optimization of a JESD204B Serial Link Reference Design

Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00153 — JESD204B Link Latency Design Using a High Speed ADC

JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
WQFN (RME) 56 View options

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