Home Clocks & timing Clock buffers
Home
Clocks & timing
Clock buffers

LMK00338

ACTIVE

8-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator

Order now
Data sheet

LMK00338

ACTIVE
Data sheet Order now

Product details

Function Differential, Fanout, Level translator Additive RMS jitter (typ) (fs) 30 Output frequency (max) (MHz) 400 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features PCIe Gen 5 Compliant Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
Function Differential, Fanout, Level translator Additive RMS jitter (typ) (fs) 30 Output frequency (max) (MHz) 400 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features PCIe Gen 5 Compliant Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
WQFN (RTA) 40 36 mm² 6 x 6
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 4 Differential Outputs Each
    • HCSL, or Hi-Z (Selectable per Bank)
    • Additive RMS Phase Jitter for PCIe Gen5 at 100 MHz:
      • 15 fs RMS (Typical)
  • –72 dBc at 156.25 MHz
  • LVCMOS Output With Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 40-lead WQFN (6 mm × 6 mm)
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 4 Differential Outputs Each
    • HCSL, or Hi-Z (Selectable per Bank)
    • Additive RMS Phase Jitter for PCIe Gen5 at 100 MHz:
      • 15 fs RMS (Typical)
  • –72 dBc at 156.25 MHz
  • LVCMOS Output With Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 40-lead WQFN (6 mm × 6 mm)

The LMK00338 device is an 8-output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00338 operates from a 3.3-V core supply and 3 independent 3.3-V or 2.5-V output supplies.

The LMK00338 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00338 device is an 8-output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00338 operates from a 3.3-V core supply and 3 independent 3.3-V or 2.5-V output supplies.

The LMK00338 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
open-in-new Find other Clock buffers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare products
Same functionality with different pin-out to the compared device.
CDCDB800 ACTIVE 8-output clock buffer for PCIe® Gen 1 to Gen 6 DB800ZL compliant with individual output enable/disable, programmable slew rate, and programmable output termination. Lacking input MUX
Similar functionality to the compared device.
LMK00308 ACTIVE 3.1-GHz differential clock buffer/level translator with 8 configurable outputs Low additive jitter ,1:8 Universal differential buffer that can support HCSL

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 3
Type Title Date
* Data sheet LMK00338 8-Output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Clock Buffer and Level Translator datasheet (Rev. C) PDF | HTML 12 Jul 2021
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
EVM User's guide LMK00338EVM User's Guide 13 Dec 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK00338EVM — LMK00338 PCIe Gen1/2/3 Clock Buffer Evaluation Module

The LMK00338 is a 400MHz, 8-output HCSL buffer intended for PCIe Gen1/2/3 Applications, low additive jitter clock distribution and level translation. The EVM allows the user to verify the functionality and performance specification of the device. Refer to the LMK00338 datasheet for the functional (...)

User guide: PDF
Not available on TI.com
Simulation model

LMK00338 IBIS Model

SNAM161.ZIP (107 KB) - IBIS Model
Download
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins Download
WQFN (RTA) 40 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos