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LMK04832-SP

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Space grade ultra low-Noise JESD204B compliant clock jitter cleaner

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Data sheet
Space grade ultra low-Noise JESD204B compliant clock jitter cleaner

LMK04832-SP

ACTIVE
Data sheet Order now

Product details

Function Single-loop PLL Number of outputs 15 RMS jitter (fs) 54 Output frequency (Max) (MHz) 3255 Input type LVCMOS, LVDS, LVPECL Output type CML, LVPECL, LCPECL, HSDS, LVDS, LVCMOS Supply voltage (Min) (V) 3.135 Supply voltage (Max) (V) 3.465 Features JESD204B Operating temperature range (C) -55 to 125, 25 to 25
Function Single-loop PLL Number of outputs 15 RMS jitter (fs) 54 Output frequency (Max) (MHz) 3255 Input type LVCMOS, LVDS, LVPECL Output type CML, LVPECL, LCPECL, HSDS, LVDS, LVCMOS Supply voltage (Min) (V) 3.135 Supply voltage (Max) (V) 3.465 Features JESD204B Operating temperature range (C) -55 to 125, 25 to 25
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CFP (HSL) (HBE) 64 119 mm² 10.9 x 10.9 CFP (HSL) (HBE) 64 —
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  • SMD #5962R1723701VXC
    • Total ionizing dose 100 krad (ELDRS-free)
    • SEL immune >120 MeV × cm2/mg
    • SEFI immune >120 MeV × cm2/mg
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKout divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clock and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • Ambient temperature range: –55 °C to 125 °C
  • SMD #5962R1723701VXC
    • Total ionizing dose 100 krad (ELDRS-free)
    • SEL immune >120 MeV × cm2/mg
    • SEFI immune >120 MeV × cm2/mg
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKout divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clock and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • Ambient temperature range: –55 °C to 125 °C
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The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The LMK04832-SP can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows the LMK04832-SP to provide flexible high performance clocking trees.

The LMK04832-SP comes in a 10.9-mm × 10.9-mm, 64-pin CFP package.

The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The LMK04832-SP can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows the LMK04832-SP to provide flexible high performance clocking trees.

The LMK04832-SP comes in a 10.9-mm × 10.9-mm, 64-pin CFP package.

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Technical documentation

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Type Title Date
* Data sheet LMK04832-SP Space Grade Ultra Low-Noise JESD204B Dual Loop Clock Jitter Cleaner datasheet (Rev. B) 18 Dec 2020
* Radiation & reliability report LMK04832-SP Single-Event Effects Report 13 May 2021
* Radiation & reliability report LMK04832-SP ELDRS Characterization Report 19 Nov 2020
* Radiation & reliability report LMK04832-SP TID RLAT Report V009FOGX Wafer 21 19 Nov 2020
More literature Total Ionizing Dose and Single Event Effects Test Results of LMK04832-SP 18 Jul 2021
Selection guide TI Space Products (Rev. H) 27 Jan 2021
User guide LMK04832EVM-CVAL User’s Guide 29 Jun 2020
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations 18 May 2020
Application note Single-Event Effects Confidence Interval Calculations 14 Jan 2020
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing 17 Jun 2019
E-book Radiation Handbook for Electronics (Rev. A) 21 May 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK04832EVM-CVAL — LMK04832-SP space grade ultra-low-noise JESD204B dual-loop clock jitter cleaner evaluation module

The LMK04832EVM-CVAL evaluation module (EVM) provides a platform to evaluate the performance and
features of the LMK04832-SP space grade ultra-low-noise JESD204B dual-loop clock jitter cleaner
from Texas Instruments.
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Support software

TICS Pro Software v1.7.2 (Rev. AL)

SNAC072AL.ZIP (61999 KB)
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Simulation model

LMK04832-SP IBIS model

SNAM242.ZIP (157 KB) - IBIS Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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CFP (HBE) 64 View options

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