Ultra-low jitter single channel network synchronizer clock with BAW
Product details
Parameters
Package | Pins | Size
Features
- One Digital Phase-Locked Loop (DPLL) With:
- Hitless Switching: ±50-ps Phase Transient
- Programmable Loop Bandwidth With Fastlock
- Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
- Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
- 50-fs RMS Jitter at 312.5 MHz (APLL1)
- 125-fs RMS Jitter at 155.52 MHz (APLL2)
- Two Reference Clock Inputs
- Priority-Based Input Selection
- Digital Holdover on Loss of Reference
- Eight Clock Outputs With Programmable Drivers
- Up to Six Different Output Frequencies
- AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V LVCMOS Output Formats
- EEPROM / ROM for Custom Clocks on Power-Up
- Flexible Configuration Options
- 1 Hz (1 PPS) to 800 MHz on Input and Output
- XO/TCXO/OCXO Input: 10 to 100 MHz
- DCO Mode: < 0.001 ppb/Step for Precise Clock Steering (IEEE 1588 PTP Slave)
- Advanced Clock Monitoring and Status
- I2C or SPI Interface
- PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
- 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
- Industrial Temperature Range: –40°C to +85°C
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Description
The LMK05318 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.
The device can generate output clocks with 50-fs RMS jitter using TIs proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.
The DPLL supports programmable loop bandwidth for jitter and wander attenuation, while the two APLLs support fractional frequency translation for flexible clock generation. The synchronization options supported on the DPLL include hitless switching with phase cancellation, digital holdover, and DCO mode with less than 0.001-ppb (part per billion) frequency step size for precision clock steering (IEEE 1588 PTP slave). The DPLL can phase-lock to a 1-PPS (pulse-per-second) reference input and support optional zero-delay mode on one output to achieve deterministic input-to-output phase alignment with programmable offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.
The device can use a commonly available low-frequency TCXO or OCXO to set the free-run or holdover output frequency stability per synchronization standards. Otherwise, the device can use a standard XO when free-run or holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power up with the internal EEPROM or ROM. The EEPROM is factory pre-programmed and can be programmed in-system if needed.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains datasheet (Rev. A) | Dec. 10, 2018 |
Technical article | Solving synchronization challenges in Industrial Ethernet | Jul. 19, 2019 | |
User guide | LMK05318 Registers (Rev. A) | Jul. 08, 2019 | |
Technical article | TI BAW resonator innovation puts time on your side | Mar. 05, 2019 | |
Technical article | Are you ready for BAW? | Feb. 27, 2019 | |
Application note | ITU-T G.8262 compliance test results for the LMK05318 (Rev. A) | Feb. 22, 2019 | |
Application note | Supported synchronization modes for TI network synchronizers (Rev. A) | Feb. 22, 2019 | |
Application note | Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) | Feb. 22, 2019 | |
White paper | TI BAW technology enables ultra-low jitter clocks for high-speed networks | Feb. 17, 2019 | |
Application note | How to use the LMK05318 as a jitter cleaner | Jan. 16, 2019 | |
User guide | LMK05318EVM User Guide (Rev. A) | Dec. 06, 2018 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping. SMA ports provide access to the LMK05318 clock inputs and outputs for (...)
Features
- One Digital PLL (DPLL) with programmable bandwidths and Two Fractional Analog PLLs (APLLs) for Flexible Clock Generation
- Two reference inputs to the DPLL supporting hitless switching & holdover
- Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
- On-chip EEPROM for custom start-up clock (...)
Software development
Features
- Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
- Export programming configurations for use in end application.
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RGZ) | 48 | View options |
Ordering & quality
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- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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