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EVALUATION BOARD Download 399
EVALUATION BOARD Download 399
The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)
- Dual DPLLs with programmable bandwidths and Analog PLLs for frequency translation
- 4 clock inputs supporting hitless switching and holdover
- 8 differential or 16 LVCMOS output clocks or combination of both
- On-chip EEPROM for custom start-up clock clocks
- Flexible oscillator options: onboard XOs, TCXO, or (...)
EVALUATION BOARD Download 99
The LMK05318EVM is an evaluation module for the LMK05318 Network Synchronizer Clock device.
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping. SMA ports provide access to the LMK05318 clock inputs and outputs for (...)
- One Digital PLL (DPLL) with programmable bandwidths and Two Fractional Analog PLLs (APLLs) for Flexible Clock Generation
- Two reference inputs to the DPLL supporting hitless switching & holdover
- Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
- On-chip EEPROM for custom start-up clock (...)
SOFTWARE PROGRAMMING TOOL Download
The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.
The LMK61E2EVM can be (...)
- Ultra low jitter differential clock generation
- Powered over USB or externally (SMA connector)
- Onboard USB to I2C interface
- Coarse and Fine Frequency margining
- GUI platform for full access to LMK03328 registers and EEPROM
SNAC074.ZIP (3782 KB) SIMULATION MODEL Download
SLYM078.ZIP (16 KB) - IBIS Model SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
DESIGN TOOL Download
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
Clock tree architect programming software
CLOCK-TREE-ARCHITECT — Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
- Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
- Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
- Presents clear and intuitive block (...)
Many TI reference designs include the LMK61E2 Use our reference design selection tool to review and identify designs that best match your application and parameters.