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LMX1860-SEP

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Rad tolerant 15GHz RF buffer, multiplier, divider with SYSREF (JESD204B/C support) and FPGA clock

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Data sheet

LMX1860-SEP

ACTIVE
Data sheet Order now

Product details

Integrated VCO No Output frequency (min) (MHz) 300 Output frequency (max) (MHz) 12800 Current consumption (mA) 405 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Radiation hardened, Ultra-low additive jitter Rating Space Operating temperature range (°C) -55 to 125 Lock time (µs) (typ) (s) Loop BW dependent
Integrated VCO No Output frequency (min) (MHz) 300 Output frequency (max) (MHz) 12800 Current consumption (mA) 405 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Radiation hardened, Ultra-low additive jitter Rating Space Operating temperature range (°C) -55 to 125 Lock time (µs) (typ) (s) Loop BW dependent
HTQFP (PAP) 64 144 mm² 12 x 12
  • VID #V62/24630
    • Total ionizing dose 30krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 43MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 43MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and 8
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature
  • High Reliability
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Extended Product Life Cycle
    • Product Traceability
  • VID #V62/24630
    • Total ionizing dose 30krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 43MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 43MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and 8
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature
  • High Reliability
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Extended Product Life Cycle
    • Product Traceability

The LMX1860-SEP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.

The LMX1860-SEP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.
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Technical documentation

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Type Title Date
* Data sheet LMX1860-SEP Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider datasheet PDF | HTML 19 Jun 2024
* Radiation & reliability report LMX1860-SEP Process Flow and Reliability Report (Rev. A) PDF | HTML 05 Aug 2024
* Radiation & reliability report LMX1860-SEP Single-Event Effects Report PDF | HTML 03 Apr 2024
* Radiation & reliability report LMX1860-SEP Total Ionizing Dose (TID) Radiation Report 03 Apr 2024
EVM User's guide LMX1860-SEP Evaluation Module User's Guide PDF | HTML 02 May 2024

Design & development

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Evaluation board

LMX1860SEPEVM — LMX1860-SEP evaluation module

The LMX1860-SEP evaluation module (EVM) is designed to evaluate the performance of the LMX1860-SEP, which is a four-output, ultra-low additive jitter radio-frequency (RF) buffer, divider and multiplier. This EVM can buffer RF clocking inputs up to 18GHz, multiply by two, by three or by four in the (...)

User guide: PDF | HTML
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HTQFP (PAP) 64 Ultra Librarian
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