SN54HC126

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Military 4-ch, 2-V to 6-V buffers with 3-state outputs

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Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 4 IOL (Max) (mA) 6 ICC (Max) (uA) 80 IOH (Max) (mA) -6 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns) Data rate (Mbps) 56 Rating Catalog, Military open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

CDIP (J) 14 130 mm² 19.94 x 6.73 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other Non-Inverting buffer/driver

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 11 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

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Description

These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54HC126, SN74HC126 datasheet (Rev. E) Jul. 28, 2003
* SMD SN54HC126 SMD 5962-86848 Jun. 21, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 14 View options
LCCC (FK) 20 View options

Ordering & quality

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