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SN54HC153

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Dual 4-Line To 1-Line Data Selectors/Multiplexers

Data sheet
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Dual 4-Line To 1-Line Data Selectors/Multiplexers

SN54HC153

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Product details

Parameters

Technology Family HC Function Digital Multiplexer Configuration 4:1 Channels (#) 2 Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Input type Standard CMOS Output type Push-Pull Data rate (Max) (Mbps) 58 ICC (Max) (uA) 160 open-in-new Find other Encoders & decoders

Package | Pins | Size

CDIP (J) 16 135 mm² 19.65 x 6.92 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other Encoders & decoders

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 9 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Permit Multiplexing from n Lines to One Line
  • Perform Parallel-to-Serial Conversion
  • Strobe (Enable) Line Provided for Cascading (N Lines to n Lines)
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Description

Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54HC153, SN74HC153 datasheet (Rev. D) Oct. 02, 2003
* SMD SN54HC153 SMD 84093012A Jun. 21, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
LCCC (FK) 20 View options

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