Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • 8-bit serial-in, parallel-out shift
  • Wide operating voltage range of 2 V to 6 V
  • High-current 3-state outputs can drive up to 15 LSTTL loads
  • Low power consumption: 80-µA (maximum) ICC
  • tpd = 13 ns (typical)
  • ±6-mA output drive at 5 V
  • Low input current: 1 µA (maximum)
  • Shift register has direct clear
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • 8-bit serial-in, parallel-out shift
  • Wide operating voltage range of 2 V to 6 V
  • High-current 3-state outputs can drive up to 15 LSTTL loads
  • Low power consumption: 80-µA (maximum) ICC
  • tpd = 13 ns (typical)
  • ±6-mA output drive at 5 V
  • Low input current: 1 µA (maximum)
  • Shift register has direct clear
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

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Technical documentation

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Type Title Date
* Data sheet SNx4HC595 8-Bit Shift Registers With 3-State Output Registers datasheet (Rev. J) PDF | HTML 07 Oct 2021
* SMD SN54HC595 SMD 5962-86816 21 Jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

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CDIP (J) 16 View options
LCCC (FK) 20 View options

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