Packaging information
| Package | Pins TSSOP (PW) | 14 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the SN54SC2T74-SEP
- Vendor item drawing available, VID V62/23632-01XE
- Total ionizing dose characterized at 30 krad (Si)
- Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
- Single-event effects (SEE) characterized:
- Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
- Single event transient (SET) characterized to 43 MeV-cm2 /mg
- Wide operating range of 1.2 V to 5.5 V
- Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
- TTL compatible inputs:
- Up translation:
- 1.8-V – Inputs from 1.2 V
- 2.5-V – Inputs from 1.8 V
- 3.3-V – Inputs from 1.8 V, 2.5 V
- 5.0-V – Inputs from 2.5 V, 3.3 V
- Down translation:
-
1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V
- 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
- 2.5-V – Inputs from 3.3 V, 5.0 V
- 3.3-V – Inputs from 5.0 V
-
- Up translation:
- TTL compatible inputs:
- 5.5 V tolerant input pins
- Output drive up to 25 mA AT 5-V
- Latch-up performance exceeds 250 mA per JESD 17
- Space enhanced plastic (SEP)
- Controlled baseline
- Gold bondwire
- NiPdAu lead finish
- One assembly and test site
- One fabrication site
- Military (–55°C to 125°C) temperature range
- Extended product life cycle
- Product traceability
- Meets NASAs ASTM E595 outgassing specification
Description for the SN54SC2T74-SEP
The SN54SC2T74-SEP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).