Product details


Function Receiver, Translator Protocols LVPECL, LVDS Number of Tx 0 Number of Rx 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 600 Input signal LVPECL, LVDS Output signal LVTTL, CMOS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 4.9 x 3.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs


  • Dual 3.3 V Differential LVPECL/LVDS to
    LVTTL/LVCMOS Buffer Translator
  • 24 mA LVTTL Ouputs
  • Operating Range
    • VCC = 3.0 V to 3.6 V
    • GND = 0 V
  • Support for Clock Frequencies > 300 MHz
  • 2.0 ns Typical Propagation Delay
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100EPT23
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

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The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device. The device includes circuitry to maintain inputs at Vcc/2 when left open. The SN65EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option.

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Technical documentation

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Type Title Date
* Datasheet 3.3-V ECL Differential Receiver datasheet (Rev. A) Jan. 27, 2011
Application notes AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct. 17, 2007

Design & development

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Design tools & simulation

SLLM146.ZIP (16 KB) - IBIS Model
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

Ordering & quality

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