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Product details

Parameters

Function Receiver, Repeater Protocols LVDS Number of Tx 4 Number of Rx 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Receiver and Drivers Meet or Exceed the
    Requirements of ANSI EIA/TIA-644 Standard
    • SN65LVDS105 Receives Low-Voltage TTL
      (LVTTL) Levels
    • SN65LVDS104 Receives Differential Input
      Levels, ±100 mV
  • Typical Data Signaling Rates to 400 Mbps or
    Clock Frequencies to 400 MHz
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical
    Output Voltage of 350 mV and a 100-Ω Load
  • Propagation Delay Time
    • SN65LVDS105 – 2.2 ns (Typ)
    • SN65LVDS104 – 3.1 ns (Typ)
  • LVTTL Levels Are 5-V Tolerant
  • Electrically Compatible With LVDS, PECL,
    LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
    SSTL, or HSTL Outputs With External Networks
  • Driver Outputs Are High-Impedance When
    Disabled or With VCC <1.5 V
  • Bus-Pin ESD Protection Exceeds 16 kV
  • SOIC and TSSOP Packaging
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Description

The SN65LVDS10x are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.

The SN65LVDS10x are characterized for operation from –40°C to 85°C.

The SN65LVDS10x are members of a family of LVDS repeaters. A brief overview of the family is provided in the Selection Guide to LVDS Repeaters section.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet (Rev. G) Dec. 31, 2015
Application notes AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct. 17, 2007
Application notes DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Feb. 19, 2003

Design & development

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Design tools & simulation

SIMULATION MODELS Download
SLLC091B.ZIP (22 KB) - IBIS Model
SIMULATION TOOLS Download
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
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SIMULATION TOOLS Download
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TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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SOIC (D) 16 View options
TSSOP (PW) 16 View options

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