Product details

IOL (Max) (mA) 64 IOH (Max) (mA) -32 Technology Family ABT Rating Catalog Operating temperature range (C) -40 to 85
IOL (Max) (mA) 64 IOH (Max) (mA) -32 Technology Family ABT Rating Catalog Operating temperature range (C) -40 to 85
SOIC (DW) 24 160 mm² 15.5 x 10.3 SSOP (DB) 24 64 mm² 8.2 x 7.8
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

EPIC-IIB is a trademark of Texas Instruments Incorporated.

  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

EPIC-IIB is a trademark of Texas Instruments Incorporated.

The 'ABT657A transceivers have eight noninverting buffers with parity-generator/
checker circuits and control signals. The transmit/receive (T/R\) input determines the direction of data flow. When T/R\ is high, data flows from the A port to the B port (transmit mode); when T/R\ is low, data flows from the B port to the A port (receive mode). When the output-enable (OE\) input is high, both the A and B ports are in the high-impedance state.

Odd or even parity is selected by a logic high or low level on the ODD/EVEN\ input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.

In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN\. For example, if ODD/EVEN\ is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.

In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR\) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN\ is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR\ is low, indicating a parity error.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT657A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT657A is characterized for operation from -40°C to 85°C.

The 'ABT657A transceivers have eight noninverting buffers with parity-generator/
checker circuits and control signals. The transmit/receive (T/R\) input determines the direction of data flow. When T/R\ is high, data flows from the A port to the B port (transmit mode); when T/R\ is low, data flows from the B port to the A port (receive mode). When the output-enable (OE\) input is high, both the A and B ports are in the high-impedance state.

Odd or even parity is selected by a logic high or low level on the ODD/EVEN\ input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.

In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN\. For example, if ODD/EVEN\ is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.

In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR\) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN\ is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR\ is low, indicating a parity error.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT657A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT657A is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet Octal Transceivers With Parity Generators/Checkers And 3-State Outputs datasheet (Rev. E) 01 Jun 1997
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 16 Feb 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 01 Mar 1997
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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SOIC (DW) 24 View options
SSOP (DB) 24 View options

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