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Product details

Parameters

Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Data rate (Mbps) 180 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other Non-Inverting buffer/driver

Features

  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 9.5 ns at 5 V
  • Inputs are TTL Compatible
  • On Products Compliant to MIL-PRF-38535,
    All Parameters are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
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Description

These SNx4ACT244 octal buffers and drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SNx4ACT244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes non-inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SNx4ACT244 Octal Buffers and Drivers With 3-State Outputs datasheet (Rev. D) Aug. 25, 2016
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCAM015A.ZIP (19 KB) - IBIS Model
SIMULATION MODELS Download
SCAM122.ZIP (7 KB) - PSpice Model
SIMULATION MODELS Download
SCEJ183.ZIP (127 KB) - HSpice Model

Reference designs

REFERENCE DESIGNS Download
Three-phase inverter reference design for 200-480 VAC drives with opto-emulated input gate drivers
TIDA-010025 — This reference design realizes a reinforced isolated three-phase inverter subsystem using isolated IGBT gate drivers and isolated current/voltage sensors. The UCC23513 gate driver used has a 6-pin wide body package with optical LED emulated inputs which enables its use as pin-to-pin replacement to (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options

Ordering & quality

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