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SN74AHC125

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4-ch, 2-V to 5.5-V buffers with 3-state outputs

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Data sheet

SN74AHC125

ACTIVE
Data sheet Order now

Product details

Technology Family AHC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 IOL (Max) (mA) 8 ICC (Max) (uA) 40 IOH (Max) (mA) -8 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
Technology Family AHC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 IOL (Max) (mA) 8 ICC (Max) (uA) 40 IOH (Max) (mA) -8 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5
  • Operating Range: 2 V to 5.5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Four Individual Output Enable Pins
  • All Inputs Have Schmitt-Trigger Action
  • Operating Range: 2 V to 5.5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Four Individual Output Enable Pins
  • All Inputs Have Schmitt-Trigger Action

The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Technical documentation

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Type Title Date
* Data sheet SNx4AHC125 Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. L) PDF | HTML 29 Nov 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

document-pdfAcrobat User guide
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Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Not available on TI.com
Simulation model

SN74AHC125 IBIS Model SN74AHC125 IBIS Model

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Simulation model

SN74AHC125 Behavioral SPICE Model SN74AHC125 Behavioral SPICE Model

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Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

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