SN74AHC1G32

ACTIVE

Single 2-input, 2-V to 5.5-V OR gate

Top

Product details

Parameters

Technology Family AHC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) -8 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 110 Rating Catalog Operating temperature range (C) -40 to 125, -40 to 85 open-in-new Find other OR gate

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 open-in-new Find other OR gate

Features

  • Operating Range of 2 V to 5.5 V
  • Max tpd of 6.5 ns at 5 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 5 V
  • Schmitt-Trigger Action at All Inputs Makes the Circuit Tolerant for Slower Input Rise and Fall Time
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
open-in-new Find other OR gate

Description

The SN74AHC1G32 device is a single 2-input positive-OR gate. The device performs the Boolean function Y = A + B or Y = A\ + B\ in positive logic.

open-in-new Find other OR gate
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 23
Type Title Date
* Data sheet SN74AHC1G32 Single 2-Input Positive-OR Gate datasheet (Rev. P) Feb. 02, 2017
Technical article How to keep your motor running safely Jun. 04, 2020
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) Apr. 01, 1998
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCLM006.ZIP (13 KB) - IBIS Model
SIMULATION MODEL Download
SCLM040.ZIP (6 KB) - IBIS Model
SIMULATION MODEL Download
SCLM041.ZIP (5 KB) - IBIS Model
SIMULATION MODEL Download
SCLM042.ZIP (6 KB) - IBIS Model
SIMULATION MODEL Download
SCLM043.ZIP (5 KB) - IBIS Model
SIMULATION MODEL Download
SCLM268.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
Thermal Printing with the PRU-ICSS on the BeagleBone Black Reference Design
TIDEP0056 The Programmable Realtime Unit – Industrial Communications Sub-System (PRU-ICSS) is a versatile component of the AM335x SoC that enables real-time, deterministic, fast GPIO control, even when running a non-deterministic operating system. This reference design provides a concrete use case and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Simple 6-Channel Power Supply Sequencing Reference Design for Multi-rail Outputs
PMP10711 PMP10711 is a 6-channel power supply sequencer that utilizes two LM3880 3-channel sequencer ICs. The design uses an external AND gate and OR gate to power up and power down all 6 channels in sequential fashion. This is useful in cases when up to 6 power rails need to be sequenced during power up and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SC70 (DCK) 5 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos