Dual 2-Line to 4-Line Decoders/Demultiplexers
Product details
Parameters
Package | Pins | Size
Features
- Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
- Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
Description
The ´ALS139 are dual 2-line to 4-line decoders/demultiplexers designed for use in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these devices can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. Therefore, the effective system delay introduced by the Schottky-clamped system decoder is negligible.
The ´ALS139 comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G\) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and simplify system design.
The SN54ALS139 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS139 is characterized for operation from 0°C to 70°C.
Technical documentation
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | Dual 2-Line To 4-Line Decoders/Demultiplexers datasheet (Rev. A) | Dec. 01, 1994 |
| Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
| User guide | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
| More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | Aug. 29, 2002 | |
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | Aug. 01, 1997 | |
| Application note | Designing With Logic (Rev. C) | Jun. 01, 1997 | |
| Application note | Input and Output Characteristics of Digital Integrated Circuits | Oct. 01, 1996 | |
| Application note | Live Insertion | Oct. 01, 1996 | |
| Application note | Advanced Schottky (ALS and AS) Logic Families | Aug. 01, 1995 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 16 | View options |
| SO (NS) | 16 | View options |
| SOIC (D) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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