These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock.
The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). ACLR\ (direct clear) overrides all other functions of the device, while SCLR\ overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD\) or by the combination of a low level at synchronous load (SLOAD\) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR\, ALOAD\, SCLR\, and SLOAD\ are all high.
A high level at the output-enable (
) input forces the Q outputs into
the high-impedance state, and a low level enables those outputs.
Counting is independent of OE\. ENT is fed forward to enable the
ripple-carry output (RCO) to produce a high-level pulse while the
count is maximum (15). The clocked carry output (CCO) produces a
high-level pulse for a duration equal to that of the low level of the
clock when RCO is high and the counter is enabled (ENP and ENT are
high); otherwise, CCO is low. CCO does not have the glitches commonly
associated with a ripple-carry output. Cascading is normally
accomplished by connecting RCO or CCO of the first counter to ENT of
the next counter. However, for very high-speed counting, RCO should
be used for cascading because CCO does not become active until the
clock returns to the low level.
The SN54ALS561A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Synchronous 4-Bit Counters With 3-State Outputs datasheet (Rev. A) | 01 Jan 1995 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 Aug 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
| Application note | Live Insertion | 01 Oct 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 Aug 1995 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 20 | View options |
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