SN74ALVCH32973

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16-Bit Bus Transceiver and Transparent D-Type Latch with 8 Independent Buffers

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Features

  • Member of the Texas Instruments Widebus+™ Family
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus+ is a trademark of Texas Instruments.

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Description

This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type latch, designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication between the A and B data bus, and the address signals are latched and buffered on the Q bus. The control-function implementation minimizes external timing requirements.

This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable (TOE)\ input can be used to disable the transceivers so that the A and B buses effectively are isolated.

When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE)\ input can be used to place the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, LOE\ and TOE\ should be tied to VCC through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of the drivers.

The eight independent noninverting buffers perform the Boolean function Y = D, and are independent of the state of DIR, TOE\, LE, and LOE\.

The A and B I/Os, and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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Technical documentation

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Type Title Date
* Datasheet SN74ALVCH32973 datasheet (Rev. C) Aug. 27, 2004
Application notes An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep. 17, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guides ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application notes TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application notes Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

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SIMULATION MODELS Download
SCEJ148.ZIP (55 KB) - HSpice Model
SIMULATION MODELS Download
SCEM336B.ZIP (160 KB) - IBIS Model

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