Product details

Technology Family AUP Supply voltage (Min) (V) 0.8 Supply voltage (Max) (V) 3.6 Number of channels (#) 2 Inputs per channel 2 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 100 Rating Catalog
Technology Family AUP Supply voltage (Min) (V) 0.8 Supply voltage (Max) (V) 3.6 Number of channels (#) 2 Inputs per channel 2 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 100 Rating Catalog
DSBGA (YFP) 8 0 mm² .8 x 1.6 UQFN (RSE) 8 2 mm² 2 x 1.5 VSSOP (DCU) 8 6 mm² 2 x 3.1 X2SON (DQE) 8 1 mm² 1.4 x 1
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5.9 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

NanoStar Is a trademark of Texas Instruments

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5.9 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

NanoStar Is a trademark of Texas Instruments

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet SN74AUP2G00 Low-Power Dual 2-Input Positive-NAND Gate datasheet (Rev. C) 07 May 2010
Application note Catch a Digital Signal PDF | HTML 16 Jul 2021
Application note Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

SN74AUP2G00 Behavioral SPICE Model

SCEM682.ZIP (7 KB) - PSpice Model
Reference designs

TIDA-010050 — Ultra-low power water flow measurement for AMR reference design

This fully tested reference design demonstrates a low-power solution for electronic measurement of water flow through a mechanical meter and provides a single-chip platform for flow measurement and wireless communications. The design is ideal for water meter automatic meter reading (AMR) modules (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
DSBGA (YFP) 8 View options
UQFN (RSE) 8 View options
VSSOP (DCU) 8 View options
X2SON (DQE) 8 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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