SN74AUP2G04

ACTIVE

Low-Power Dual Inverter Gate

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Product details

Parameters

Technology Family AUP VCC (Min) (V) 0.8 VCC (Max) (V) 3.6 Channels (#) 2 IOL (Max) (mA) 4 IOH (Max) (mA) -4 ICC (Max) (uA) 0.9 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 200 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

DSBGA (YFP) 6 1 mm² .8 x 1.2 SOT-SC70 (DCK) 6 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DSF) 6 1 mm² 1 x 1 open-in-new Find other Inverting buffer/driver

Features

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption:
    ICC = 0.9 µA Max
  • Low Dynamic-Power Consumption:
    Cpd = 4.3 pF Typ at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typ
  • Low Noise: Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.3 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

NanoStar is a trademark of Texas Instruments

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Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 1).

The SN74AUP2G04 performs the Boolean function Y = A in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet SN74AUP2G04 Low-Power Dual Inverter Gate datasheet (Rev. B) Mar. 31, 2010
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Understanding Schmitt Triggers Sep. 21, 2011
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCEM680.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
DSBGA (YFP) 6 View options
SC70 (DCK) 6 View options
SON (DRY) 6 View options
SON (DSF) 6 View options

Ordering & quality

Support & training

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