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3.3-V, 1:1 (SPST), 4-channel FET bus switch with level shifter

SN74CB3T3125

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Product details

Parameters

Configuration 1:1 SPST Number of channels (#) 4 Power supply voltage - single (V) 2.5, 3.3 Ron (Typ) (Ohms) 5 ON-state leakage current (Max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (Max) (mA) 128 Rating Catalog CON (Typ) (pF) 4 open-in-new Find other Analog switches & muxes

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Analog switches & muxes

Features

  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation On All Data I/O Ports
    • 5-V Input Down to 3.3-V Output-Level Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output-Level Shift With 2.5-V VCC
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typical)
  • Low Input/Output Capacitance Minimizes Loading
    (Cio(OFF) = 4.5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 20 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

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Description

The SN74CB3T3125 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3125 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Typical DC Voltage-Translation Characteristics).

The SN74CB3T3125 is organized as four 1-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN74CB3T3125 Quadruple FET Bus Switch 2.5-V, 3.3-V Low-Voltage Bus Switch with 5-V-Tolerant Level Shifter datasheet (Rev. C) Dec. 20, 2018
Application notes CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. A) Jun. 30, 2020
Application notes Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application notes Multiplexers and Signal Switches Glossary Mar. 06, 2020
Technical articles Roll with the design punches and overcome power-sequencing challenges Jul. 29, 2019
Application notes Eliminate power Sequencing with powered-off protection signal switches (Rev. B) Jan. 15, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Digital Bus Switch Selection Guide (Rev. A) Nov. 10, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Bus FET Switch Solutions for Live Insertion Applications Feb. 07, 2003
Application notes CBT-C, CB3T, and CB3Q Signal-Switch Families Feb. 04, 2003

Design & development

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Hardware development

INTERFACE ADAPTERS Download
document-generic User guide
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


Design tools & simulation

SIMULATION MODELS Download
SCDM024.ZIP (26 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options
VQFN (RGY) 14 View options

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