Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
Product details
Parameters
Package | Pins | Size
Features
- Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
Description
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | Dual J-K Positive-Edge-Triggered Flip-Flops w/Clear And Preset datasheet (Rev. A) | Oct. 01, 1993 |
Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. A) | Feb. 06, 2015 | |
User guide | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
Application note | TI IBIS File Creation, Validation, and Distribution Processes | Aug. 29, 2002 | |
Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | Aug. 01, 1997 | |
Application note | Designing With Logic (Rev. C) | Jun. 01, 1997 | |
Application note | Input and Output Characteristics of Digital Integrated Circuits | Oct. 01, 1996 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
PDIP (N) | 16 | View options |
SOIC (D) | 16 | View options |
Ordering & quality
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Support & training
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