Product details

Number of channels (#) 9 Technology Family F Input type Bipolar Output type Push-Pull Features Very high speed (tpd 5-10ns)
Number of channels (#) 9 Technology Family F Input type Bipolar Output type Push-Pull Features Very high speed (tpd 5-10ns)
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8
  • Generates Either Odd or Even Parity for Nine Data Lines
  • Cascadable for N-Bits Parity
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
  • Generates Either Odd or Even Parity for Nine Data Lines
  • Cascadable for N-Bits Parity
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

These universal, monolithic, 9-bit parity generators/checkers feature odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading.

The SN54F280B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F280B is characterized for operation from 0°C to 70°C.

 

 

These universal, monolithic, 9-bit parity generators/checkers feature odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading.

The SN54F280B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F280B is characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

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Type Title Date
* Data sheet 9-Bit Parity Generators/Checkers datasheet (Rev. A) 01 Oct 1993
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

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