Product details

Technology family GTL Applications MDIO, PMBus, SDIO, SMBus Rating Catalog Operating temperature range (°C) -40 to 85
Technology family GTL Applications MDIO, PMBus, SDIO, SMBus Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 28 62.08 mm² 9.7 x 6.4
  • Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
  • Series Termination on TTL Outputs of 30
  • Latch-Up Testing Done to JEDEC Standard JESD 78
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

  • Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
  • Series Termination on TTL Outputs of 30
  • Latch-Up Testing Done to JEDEC Standard JESD 78
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The SN74GTL2007 is a 12-bit translator to interface between the 3.3-V LVTTL chip set I/O and the Xeon. processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.

The SN74GTL2007 is a 12-bit translator to interface between the 3.3-V LVTTL chip set I/O and the Xeon. processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 13
Type Title Date
* Data sheet SN74GTL2007 datasheet 23 Mar 2005
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
User guide GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) 15 Sep 2001
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application note GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) 01 Mar 1997
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Package Pins Download
TSSOP (PW) 28 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos