Product details

Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 5.2 IOH (Max) (mA) 0 Input type Standard CMOS Output type Open-Drain Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 28 Rating Catalog
Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 5.2 IOH (Max) (mA) 0 Input type Standard CMOS Output type Open-Drain Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 28 Rating Catalog
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide Operating Voltage Range: 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Maximum ICC
  • Typical tpd = 8 ns at 5 V
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA
  • Wide Operating Voltage Range: 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Maximum ICC
  • Typical tpd = 8 ns at 5 V
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA

This device contains four independent 2-input NAND Gates with open-drain outputs. Each gate performs the Boolean function Y = A ● B in positive logic.

This device contains four independent 2-input NAND Gates with open-drain outputs. Each gate performs the Boolean function Y = A ● B in positive logic.

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Technical documentation

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Type Title Date
* Data sheet SNx4HC03 Quadruple 2-Input NAND Gates with Open-Drain Outputs datasheet (Rev. F) PDF | HTML 30 Apr 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74HC03 Behavioral SPICE Model

SCLM233.ZIP (6 KB) - PSpice Model
Reference designs

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Design guide: PDF
Schematic: PDF
Reference designs

TIDM-MINI-DC — Data Concentrator Reference Design for Smaller AMI Networks Reduces Infrastructure Cost

The TIDM-MINI-DC reference design implements a light-weight powerline communication (PLC) data concentrator (DC) solution integrated with an Ethernet repeater feature. A power grid network is static, which means that once end-nodes are installed the number of nodes to be supported by a DC is (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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