Product details

Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) -1 Input type Bipolar Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 35 Rating Catalog
Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) -1 Input type Bipolar Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 35 Rating Catalog
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6
  • For Driving Low-Threshold-Voltage MOS Inputs

 

  • For Driving Low-Threshold-Voltage MOS Inputs

 

These 2-input open-collector NAND gates feature high-output voltage ratings for interfacing with low-threshold-voltage MOS logic circuits or other 12-volt systems. Although the output is rated to withstand 15 volts, the VCC terminal is connected to the standard 5-volt source.

The SN5426 and SN54LS26 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7426 and SN74LS26 are characterized for operation from 0°C to 70°C.

 

These 2-input open-collector NAND gates feature high-output voltage ratings for interfacing with low-threshold-voltage MOS logic circuits or other 12-volt systems. Although the output is rated to withstand 15 volts, the VCC terminal is connected to the standard 5-volt source.

The SN5426 and SN54LS26 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7426 and SN74LS26 are characterized for operation from 0°C to 70°C.

 

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Technical documentation

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Type Title Date
* Data sheet Quadruple 2-Input High-Voltage Interface Positive-NAND Gates datasheet 01 Mar 1988
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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Limit: 5
Simulation model

SN74LS26 Behavioral SPICE Model

SDLM040.ZIP (6 KB) - PSpice Model
Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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