SN74LV11A

ACTIVE

3-ch, 3-input, 2-V to 5.5-V AND gates

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Product details

Parameters

Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 3 Inputs per channel 3 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 70 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other AND gate

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 open-in-new Find other AND gate

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

open-in-new Find other AND gate

Description

These triple 3-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.

The ’LV11A devices perform the Boolean function Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

open-in-new Find other AND gate
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Technical documentation

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Type Title Date
* Datasheet SN54LV11A, SN74LV11A datasheet (Rev. D) Apr. 22, 2005
Technical article How to keep your motor running safely Jun. 04, 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCEM658.ZIP (8 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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