SN74LV165A-Q1

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Product details

Configuration Parallel-in, Serial-out Bits (#) 8 Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (MHz) 85 IOL (Max) (mA) 12 IOH (Max) (mA) -12 ICC (Max) (uA) 20 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff)
Configuration Parallel-in, Serial-out Bits (#) 8 Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (MHz) 85 IOL (Max) (mA) 12 IOH (Max) (mA) -12 ICC (Max) (uA) 20 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff)
WQFN (BQB) 16
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1:
      • 40°C to + 125°C, TA
    • Device HBM ESD Classifiaction Level 2
    • Device CDM ESD Classifcation Level C6
  • Available in wettable flank QFN (WBQB) package
  • 2 V to 5.5 V VCC operation
  • Maximum tpd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1:
      • 40°C to + 125°C, TA
    • Device HBM ESD Classifiaction Level 2
    • Device CDM ESD Classifcation Level C6
  • Available in wettable flank QFN (WBQB) package
  • 2 V to 5.5 V VCC operation
  • Maximum tpd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV165A-Q1 device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCC operation.

When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165A-Q1 devices features a clock-inhibit function and a complemented serial output, Q H.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The SN74LV165A-Q1 device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCC operation.

When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165A-Q1 devices features a clock-inhibit function and a complemented serial output, Q H.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Technical documentation

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* Data sheet SN74LV165A-Q1 Automotive Parallel-Load 8-Bit Shift Registers datasheet PDF | HTML 28 Jul 2022
Application note Power-Up Behavior of Clocked Devices (Rev. A) 06 Feb 2015

Design & development

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Simulation model

SN74LV165A IBIS Model (Rev. B) SN74LV165A IBIS Model (Rev. B)

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WQFN (BQB) 16 View options

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