SN74LV273A-Q1

PREVIEW

Product details

Number of channels (#) 8 Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 70 IOL (Max) (mA) 12 IOH (Max) (mA) -12 ICC (Max) (uA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)
Number of channels (#) 8 Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 70 IOL (Max) (mA) 12 IOH (Max) (mA) -12 ICC (Max) (uA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)
VQFN (RKS) 20
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1:
      • 40°C to + 125°C, TA
    • Device HBM ESD Classifiaction Level 2
    • Device CDM ESD Classifcation Level C6
  • Available in wettable flank QFN (WRKS) package
  • 2 V to 5.5 V VCC operation
  • Maximum tpd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1:
      • 40°C to + 125°C, TA
    • Device HBM ESD Classifiaction Level 2
    • Device CDM ESD Classifcation Level C6
  • Available in wettable flank QFN (WRKS) package
  • 2 V to 5.5 V VCC operation
  • Maximum tpd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low clear (CLR) input and clock (CLK).

Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or transitioning from a high level to a low level, the D input has no effect at the output. Information at the data (Q) outputs can be asynchronously cleared with a low level input through the clear (CLR) pin.

The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low clear (CLR) input and clock (CLK).

Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or transitioning from a high level to a low level, the D input has no effect at the output. Information at the data (Q) outputs can be asynchronously cleared with a low level input through the clear (CLR) pin.

Download

Similar products you might be interested in

open-in-new Compare products
Pin-for-pin with same functionality to the compared device.
SN74LV273A ACTIVE Octal D-Type Flip-Flops With Clear

Commerical product equivalent, same electrical specs and features 

Same functionality with different pin-out to the compared device.
SN74HCS273-Q1 ACTIVE Automotive octal D-type flip-flops with clear

Automotive grade product, different family, similar electrical specs and features 

SN74LVTH273-EP ACTIVE Enhanced Product 3.3-V Abt Octal D-Type Flip-Flops With Clear

Enhanced product product, different family, different electrical specs and features 

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet SN74LV273A-Q1 Automotive Octal D-Type Flip-Flops With Clear datasheet PDF | HTML 11 Aug 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV273A-Q1 IBIS Model

SCLM350.ZIP (44 KB) - IBIS Model
Package Pins Download
VQFN (RKS) 20 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos