SN74LV4066A

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5-V, 1:1 (SPST), 4-channel general-purpose analog switch (CDIP & CFP packages)

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Product details

Parameters

Configuration 1:1 SPST Number of channels (#) 4 Ron (Typ) (Ohms) 21 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 50 Operating temperature range (C) -40 to 85 Input/output continuous current (Max) (mA) 28 Rating Catalog CON (Typ) (pF) 5.5 Supply current (Typ) (uA) 1 open-in-new Find other Analog switches/muxes

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Analog switches/muxes

Features

  • 2-V to 5.5-V VCC Operation
  • Support Mixed-Mode Voltage Operation on All Ports
  • High On-Off Output-Voltage Ratio
  • Low Crosstalk Between Switches
  • Individual Switch Controls
  • Extremely Low Input Current
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

This quadruple silicon-gate CMOS analog switch is designed for 2-V to 5.5-V VCC operation.

These switches are designed to handle both analog and digital signals. Each switch permits signals with amplitudes up to 5.5 V (peak) to be transmitted in either direction.

Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

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Technical documentation

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No results found. Please clear your search and try again. View all 5
Type Title Date
* Datasheet SN54LV4066A, SN74LV4066A datasheet (Rev. I) Apr. 05, 2005
Application notes Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application notes Multiplexers and Signal Switches Glossary Mar. 06, 2020
Technical articles Roll with the design punches and overcome power-sequencing challenges Jul. 29, 2019
Technical articles Is charge injection causing output voltage errors in your industrial control system? Oct. 18, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

INTERFACE ADAPTERS Download
document-generic User guide
$10.00
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


Design tools & simulation

SIMULATION MODELS Download
SCLM096.ZIP (41 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

Support & training

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