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SN74LV4T32

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1.8-V to 5.5-V single power supply quadruple OR gates

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Data sheet

SN74LV4T32

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Data sheet Order now

Product details

Technology family LVxT Number of channels 4 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 150 IOH (max) (mA) -8 IOL (max) (mA) 8 Supply current (max) (µA) 2 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type Standard CMOS, TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -40 to 125
Technology family LVxT Number of channels 4 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 150 IOH (max) (mA) -8 IOL (max) (mA) 8 Supply current (max) (µA) 2 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type Standard CMOS, TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Wide operating range of 1.8 V to 5.5 V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:
      • 1.2 V to 1.8 V
      • 1.5 V to 2.5 V
      • 1.8 V to 3.3 V
      • 3.3 V to 5.0 V
    • Down translation:
      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17
  • Wide operating range of 1.8 V to 5.5 V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:
      • 1.2 V to 1.8 V
      • 1.5 V to 2.5 V
      • 1.8 V to 3.3 V
      • 3.3 V to 5.0 V
    • Down translation:
      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV4T32 contains four independent 2-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV4T32 contains four independent 2-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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Technical documentation

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* Data sheet SN74LV4T32 Quadruple 2-Input Positive-OR Gates With Integrated Translation datasheet PDF | HTML 18 May 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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TSSOP (PW) 14 View options
WQFN (BQA) 14 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

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