SN74LVC1G74

ACTIVE

Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset

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Product details

Parameters

Technology Family LVC Input type Standard CMOS Output type Push-Pull VCC (Min) (V) 1.65 VCC (Max) (V) 5.5 Channels (#) 1 Clock Frequency (Max) (MHz) 200 ICC (uA) 10 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff) Rating Catalog open-in-new Find other D-type flip-flop

Package | Pins | Size

SSOP (DCT) 8 8 mm² 2.95 x 2.80 UQFN (RSE) 8 2 mm² 2 x 1.5 VSSOP (DCU) 8 6 mm² 2 x 3.1 X2SON (DQE) 8 1 mm² 1.4 x 1 open-in-new Find other D-type flip-flop

Features

  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 5.9 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model

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open-in-new Find other D-type flip-flop

Description

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

open-in-new Find other D-type flip-flop
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset datasheet (Rev. F) Apr. 16, 2020
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
White papers Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) May 01, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
Technical articles How fast can it run? Determine the speed of your logic device Oct. 16, 2013
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCEM591.ZIP (52 KB) - IBIS Model

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CAD/CAE symbols

Package Pins Download
SM8 (DCT) 8 View options
UQFN (RSE) 8 View options
VSSOP (DCU) 8 View options
X2SON (DQE) 8 View options

Ordering & quality

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