SN74SSTVF16859

ACTIVE

13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs

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13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs

SN74SSTVF16859

ACTIVE

Product details

Parameters

Function Memory interface Output frequency (Max) (MHz) 500 Number of outputs 26 VCC core (V) 2.5 Features DDR register Operating temperature range (C) 0 to 70 Rating Catalog open-in-new Find other Clock buffers

Package | Pins | Size

TSSOP (DGG) 64 138 mm² 17 x 8.1 VQFNP (RGQ) 56 64 mm² 8 x 8 open-in-new Find other Clock buffers

Features

  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700
  • Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16859
  • 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications
  • 1-to-2 Outputs to Support Stacked DDR DIMMs
  • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Pinout Optimizes DIMM PCB Layout
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

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Description

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.

The SN74SSTVF16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

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Technical documentation

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Type Title Date
* Datasheet SN74SSTVF16859 datasheet (Rev. B) Jan. 30, 2004
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes 56-Pin Quad Flatpack No-Lead Logic Package Feb. 07, 2003
Application notes Application of the SN74SSTVF16857 in Planar PC2700 (DDR-333) RDIMMs Jan. 10, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature DIMM Module Solution Jun. 13, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes Application of the SN74SSTV32852 in Stacked, Low-Profile (1U) PC-1600/2100 DIMMs Nov. 07, 2001
Application notes Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 Feb. 09, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SCEJ145A.ZIP (48 KB) - HSpice Model
SIMULATION MODELS Download
SCEM341.ZIP (18 KB) - IBIS Model
SIMULATION MODELS Download
SCEM342.ZIP (18 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
TSSOP (DGG) 64 View options
VQFN (RGQ) 56 View options

Ordering & quality

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