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Product details

Parameters

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 250 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Four- (’390), Eight- (’388A), or Sixteen- (’386)
    Line Receivers Meet or Exceed the Requirements
    of ANSI TIA/EIA-644 Standard
  • Integrated 110-Ω Line Termination
    Resistors on LVDT Products
  • Designed for Signaling Rates Up to 250 Mbps
  • SN65 Versions Bus-Terminal ESD Exceeds
    15 kV
  • Operates From a Single 3.3-V Supply
  • Typical Propagation Delay Time of 2.6 ns
  • Output Skew 100 ps (Typical) Part-To-Part
    Skew Is Less Than 1 ns
  • LVTTL Levels Are 5-V Tolerant
  • Open-Circuit Fail Safe
  • Flow-Through Pinout
  • Packaged in Thin Shrink Small-Outline
    Package With 20-mil Terminal Pitch
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Description

This family of 4-, 8-, or 16-differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail.

Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, the 8- or 16-channel driver (the SN65LVDS389 or SN65LVDS387, respectively), over 200 million data transfers per second in single-edge clocked systems are possible with little power.

The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 4
Type Title Date
* Datasheet High-Speed Differential Line Receivers. datasheet (Rev. I) Jul. 29, 2014
Application notes LVDS to Improve EMC in Motor Drives Sep. 27, 2018
Application notes How Far, How Fast Can You Operate LVDS Drivers and Receivers? Aug. 03, 2018
Application notes How to Terminate LVDS Connections with DC and AC Coupling May 16, 2018

Design & development

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SOIC (D) 16 View options
TSSOP (PW) 16 View options

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