Automotive system basis chip (SBC) with integrated CAN FD controller & transceiver
Product details
Parameters
Package | Pins | Size
Features
- AEC-Q100: qualified for automotive applications
- Temperature grade 1: –40°C to 125°C TA
- Functional safety quality-managed
- Documentation available to aid functional safety system design up to ASIL-D/SIL-3
- CAN FD controller with integrated CAN FD transceiver and serial peripheral interface (SPI)
- CAN FD controller supports both ISO 11898-1:2015 and Bosch M_CAN Revision 3.2.1.1
- Meets the requirements of ISO 11898-2:2016
- Supports CAN FD data rates up to 8 Mbps with up to 18 MHz SPI clock speed
- Classic CAN backwards compatible
- Operating modes: normal, standby, sleep, and failsafe
- 3.3 V to 5 V input/output logic support for microprocessors
- Wide operating ranges on CAN bus
- ±58 V bus fault protection
- ±12 V common mode
- Integrated low drop out voltage regulator suppling 5 V to CAN transceiver and up to 70 mA for external devices
- Optimized behavior when unpowered
- Bus and logic terminals are high impedance (No load to operating bus or application)
- Power up and down glitch free operation
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Description
The TCAN4550-Q1 is a CAN FD controller with an integrated CAN FD transceiver supporting data rates up to 8 Mbps. The CAN FD controller meets the specifications of the ISO11898-1:2015 high speed controller area network (CAN) data link layer and meets the physical layer requirements of the ISO11898–2:2016 high speed CAN specification. The TCAN4550-Q1 provides an interface between the CAN bus and the system processor through serial peripheral interface (SPI), supporting both classic CAN and CAN FD, allowing port expansion or CAN support with processors that do not support CAN FD. The TCAN4550-Q1 provides CAN FD transceiver functionality: differential transmit capability to the bus and differential receive capability from the bus. The device supports wake up via local wake up (LWU) and bus wake using the CAN bus implementing the ISO11898-2:2016 Wake Up Pattern (WUP).
The device includes many protection features providing device and CAN bus robustness. These features include failsafe mode, internal dominant state timeout, wide bus operating range and a time-out watchdog as examples.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | TCAN4550-Q1 Automotive Control Area Network Flexible Data Rate (CAN FD) Controll datasheet (Rev. C) | Aug. 21, 2020 |
Technical article | How semiconductor technologies are changing automotive lighting roadmaps | Oct. 23, 2019 | |
Functional safety information | TCAN4550-Q1 Functional Safety-Manual | Jul. 23, 2019 | |
Technical article | Adding CAN nodes in Bluetooth® Low Energy PEPS systems | Jun. 11, 2019 | |
Technical article | System basis chips 101 - A beginner's guide to CAN, CAN FD and LIN SBCs | Jun. 10, 2019 | |
User guide | TCAN45xx Software User's Guide | May 03, 2019 | |
Application note | Understanding LDO Performance in the TCAN4550-Q1 | May 03, 2019 | |
Application note | TCAN4550 Watchdog Configuration Guide | May 01, 2019 | |
User guide | SPI to CAN FD SBC + LIN Transceiver BoosterPack User's Guide | Apr. 01, 2019 | |
Technical article | CAN & LIN: take a look inside | Mar. 01, 2018 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- TCAN4550-Q1 CAN FD controller with integrated transceiver and SPI interface
- TLIN2029-Q1 fault protected LIN transceiver
- TPS7B7702-Q1 automotive dual-channel LDO
- Common DB9 connector for supply voltage, CAN FD, and LIN bus signals
- Follows the BoosterPack pinout standard
Description
The EVM can be used to evaluate the TCAN4550 SPI to CAN FD Controller and Transceiver solution. The CAN bus signals are easily accessed via a DB9 connector (or via header pins), and the digital interface (SPI lines plus GPIOs) is accessible via a single dual-row header. Input clocks to (...)
Features
- Provides access to CAN bus, SPI, clock, and all GPIO signals
- Clock input can be configured for on-board crystal or external clock source
- CAN bus termination can be enabled/disabled via jumpers
- Status LEDs indicate board power status and GPIO pin states
Software development
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDA-020004 BOM.pdf (37KB) -
download TIDA-020004 Assembly Drawing.pdf (365KB) -
download TIDA-020004 PCB.pdf (3586KB) -
download TIDA-020004 CAD Files.zip (3744KB) -
download TIDA-020004 Gerber.zip (1144KB)
Design files
-
download TIDA-020032 BOM.pdf (136KB) -
download TIDA-020032 Assembly Drawing.pdf (191KB) -
download TIDA-020032 PCB.pdf (1202KB) -
download TIDA-020032 CAD Files.zip (2159KB) -
download TIDA-020032 Gerber.zip (749KB)
Design files
-
download TIDEP-01014 BOM Files.zip (161KB) -
download TIDEP-01014 Assembly Files.zip (633KB) -
download TIDEP-01014 Layer Plots.zip (1380KB) -
download TIDEP-01014 CAD Files.zip (1723KB) -
download TIDEP-01014 Gerber.zip (1125KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RGY) | 20 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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