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  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Hardware Coprocessors
    • Four Turbo Decoders
      • Supports WCDMA/HSPA/HSPA+/TD-SCDMA, LTE, LTE-A, and WiMAX
      • Supports up to 530 Mbps for LTE at Block Size 6144, 8 Iterations and up to 400 Mbps for WCDMA at Block Size 5114, 8 Iterations
      • Low DSP Overhead – Hardware Interleaver Table Generation and CRC Check
    • Eight Viterbi Decoders
      • Supports up to 96 Mbps (Length 9, Rate 1/2, Block Size 6000)
    • Four WCDMA Receive Acceleration Coprocessors
      • Supports up to 8192 Correlators
    • WCDMA Transmit Acceleration Coprocessor
      • Supports up to 2304 Spreaders
    • Six Fast Fourier Transform (FFT) Coprocessors
      • Support up to 600 Mscps/FFTC at FFT Size 1024
    • Bit Rate Coprocessor
      • WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A, and WiMAX Uplink and Downlink Bit Processing
      • Includes Encoding, Rate Matching/Dematching, Segmentation, Multiplexing, and More
      • Supports up to DL 1525 Mbps and UL 1030 (on-chip) or 680 (DDR3) Mbsp for LTE and DL 784 Mbps and UL 395 Mbsp for WCDMA/TD-SCDMA
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Sixteen Rake/Search Accelerators (RSA) for
    • Chip Rate Processing for WCDMA Rel’99, HSDPA, and HSDPA+
    • Reed-Muller Decoding
  • Peripherals
    • Six-Lane SerDes-Based Antenna Interface (AIF2)
      • Operating at up to 6.144 Gbps
      • Compliant With OBSAI RP3 and CPRI Standards for 3G and 4G (WCDMA, LTE TDD, LTE FDD, TD-SCDMA, and WiMAX)
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud, Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • Twenty 64-Bit Timers
    • Five On-Chip Phase-Locked Loops (PLLs)
  • Commercial Case Temperature:
    • 0ºC to 100ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

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The TCI6638K2K Communications Infrastructure KeyStone SoC is a member of the C66x family based on TI’s new KeyStone II Multicore SoC Architecture designed specifically for high-performance wireless infrastructure applications. The TCI6638K2K provides a very high-performance macro base station platform for developing all wireless standards, including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed I/O, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the TCI6638K2K enables the ability for layer 2 and layer 3 processing on-chip. Operations such as Traffic Control, Local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math-oriented (VPi) processing. These enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for algorithms like MIMO and beamforming.

The TCI6638K2K contains many wireless base station coprocessors to offload the bulk of the processing demands of layer 1 and layer 2 base station processing. This keeps the cores free for receiver algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC and TCP3d. A key coprocessor for enabling high data rates is the Bit Rate Coprocessor (BCP), which handles the entire downlink bit-processing chain and much of the receive bit processing. The architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse across all base station platforms from Femto to Macro.

The TCI6638K2K device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 58
Type Title Date
* Datasheet TCI6638K2K Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G) Oct. 06, 2017
* Errata TCI6638K2K Multicore DSP+ARM KeyStone II SOC Silicon Errata (Rev. F) May 16, 2017
Application notes Using Arm ROM Bootloader on Keystone II Devices Jun. 04, 2019
Application notes KeyStone II DDR3 interface bring-up Mar. 07, 2019
Application notes DDR3 Design Requirements for KeyStone Devices (Rev. C) Jan. 23, 2018
User guides KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) Aug. 21, 2017
Application notes Thermal Design Guide for DSP and Arm Application Processors (Rev. B) Aug. 14, 2017
User guides Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) Jul. 26, 2017
User guides Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) Jul. 27, 2016
Application notes Power Management of KS2 Device (Rev. C) Jul. 15, 2016
Application notes SERDES Link Commissioning on KeyStone I and II Devices Apr. 13, 2016
Technical articles Accelerating the Fast Fourier Transform (FFT/iFFT) by 10x and more Mar. 02, 2016
Application notes Throughput Performance Guide for KeyStone II Devices (Rev. B) Dec. 22, 2015
White papers Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce Dec. 17, 2015
Application notes Keystone II DDR3 Debug Guide Oct. 16, 2015
Application notes Migrating From KeyStone I to KeyStone II (Rev. A) Jul. 30, 2015
User guides Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) May 06, 2015
User guides Bit Rate Coprocessor (BCP) for KeyStone Devices User's Guide (Rev. A) Apr. 27, 2015
User guides Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) Apr. 09, 2015
User guides DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) Mar. 27, 2015
User guides Fast Fourier Transform Coprocessor (FFTC) for KeyStone II Devices User's Guide (Rev. A) Feb. 11, 2015
User guides Antenna Interface 2 (AIF2) User Guide for KeyStone II Devices (Rev. B) Feb. 06, 2015
Application notes Keystone II DDR3 Initialization Jan. 26, 2015
User guides Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) Sep. 04, 2014
User guides Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) Sep. 03, 2014
Application notes Hardware Design Guide for KeyStone II Devices Mar. 24, 2014
Application notes Ethernet Packet Transfer Via FastC&M over AIF2 Application Report Dec. 06, 2013
User guides PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) Sep. 30, 2013
User guides Debug and Trace for KeyStone II Devices User's Guide Jul. 26, 2013
User guides ARM Bootloader User Guide for KeyStone II Devices Jul. 21, 2013
User guides DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) Jul. 15, 2013
User guides Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D) Jul. 03, 2013
User guides C66x CorePac User's Guide (Rev. C) Jun. 28, 2013
User guides Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) Jun. 28, 2013
User guides HyperLink for KeyStone Devices User's Guide (Rev. C) May 28, 2013
User guides 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices Feb. 08, 2013
User guides Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B) Feb. 05, 2013
User guides Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices Nov. 12, 2012
User guides ARM CorePac User Guide for KeyStone II Devices Oct. 31, 2012
Application notes Multicore Programming Guide (Rev. B) Aug. 29, 2012
User guides Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A) Jul. 11, 2012
User guides Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) Mar. 30, 2012
User guides Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) Mar. 27, 2012
User guides 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) Mar. 22, 2012
Application notes PCIe Use Cases for KeyStone Devices Dec. 13, 2011
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide Sep. 02, 2011
User guides Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A) Jun. 10, 2011
User guides External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) May 24, 2011
White papers Software and Hardware Design Challenges Due to Dynamic Raw NAND Market May 19, 2011
User guides Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide Nov. 18, 2010
User guides C66x CPU and Instruction Set Reference Guide Nov. 09, 2010
User guides C66x DSP Cache User's Guide Nov. 09, 2010
Application notes Clocking Design Guide for KeyStone Devices Nov. 09, 2010
User guides General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide Nov. 09, 2010
Application notes Optimizing Loops on the C66x DSP Nov. 09, 2010
User guides Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG Nov. 09, 2010
User guides Network Coprocessor for KeyStone Devices User's Guide Nov. 02, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


The TCI6638K2K Evaluation Module (EVM) with double wide AMC form-factor enables developers to immediately start evaluating TCI6638K2K processor and begin building application around it especially those demanding high-performance computation like telecom infrastructures, wireless standards including (...)

  • 8 TMS320C66x DSP CorePacs @ 1GHz and 1.2GHz
  • 4 ARM Cortex A15 CorePacs @ 1GHz and 1.2GHz

Software development

Azcom LTE Stack
Provided by Azcom Technology — Azcom Technology, head quartered in Milan, Italy, is amongst the leading players in advanced wireless communications for the past two decades.

Azcom provides a wide range of solutions and services for TI TCI6638K2K, and TCI6630K2L platforms. Solutions include carrier grade PHY and Layer 2/3 stack for (...)
CommAgility Small Cell
Provided by CommAgility CommAgility is an award-winning, world-leading developer of embedded signal processing and RF modules, and LTE PHY/stack software, for 4G and 5G mobile network and related applications. Our products and technology are used in the most demanding real time signal processing, test and control (...)
C6000 code generation tools - compiler
C6000-CGT — The TI C6000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C6000 Digital Signal Processor platforms, including the C66x multi-core, C674x and C64x+ single-core Digital Signal Processors.
  • Available in C6000 Code Generation Tools starting with v8.3.0:
    • Supports the C++14 Standard ISO/IEC 14882:2014 (C++03 is no longer supported)
  • Available in C6000 Code Generation Tools starting with release v8.2.0:
    • Conversion of floating-point values to unsigned char or short no longer generate RTS (...)
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Multicore Processors

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

Design tools & simulation

SPRM576A.ZIP (18 KB) - BSDL Model
SPRM577A.ZIP (19 KB) - BSDL Model
SPRM587.ZIP (2384 KB) - IBIS Model
SPRM659A.ZIP (163 KB) - Power Model
SPRM743.ZIP (265889 KB) - IBIS-AMI Model
SPRR186.ZIP (3 KB)
SPRR187.ZIP (116 KB)

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