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Product details

Parameters

Function Zero-delay Output frequency (Max) (MHz) 110 Number of outputs 2 VCC core (V) 3.3, 5 Operating temperature range (C) -20 to 75 Rating Catalog open-in-new Find other Clock buffers

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Clock buffers

Features

  • VCO (Voltage-Controlled Oscillator):
    • Complete Oscillator Using Only One External Bias Resistor (RBIAS)
    • Lock Frequency:
      • 30 MHz to 55 MHz (VDD = 3 V ±5%, TA = -20°C to 75°C, x1 Output)
      • 30 MHz to 60 MHz (VDD = 3.3 V ±5%, TA = -20°C to 75°C, x1 Output)
      • 43 MHz to 110 MHz (VDD = 5 V ±5%, TA = -20°C to 75°C, x1 Output)
    • Selectable Output Frequency
  • PFD (Phase Frequency Detector): High Speed, Edge-Triggered Detector with Internal Charge Pump
  • Independent VCO, PFD Power-Down Mode
  • Thin Small-Outline Package (14 Terminal)
  • CMOS Technology
  • Pin Compatible TLC2933IPW

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Description

The TLC2933A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage. The high speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions, which can be used as power-down mode. Due to the TLC2933A high speed and stable oscillation capability, the TLC2933A is suitable for use as a high-performance PLL.

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Technical documentation

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Type Title Date
* Datasheet High Performance Phase Locked Loop datasheet Oct. 10, 2005

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TSSOP (PW) 14 View options

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