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TMS320TCI6488

NOT RECOMMENDED FOR NEW DESIGNS

Communications infrastructure digital signal processor

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Data sheet
Errata

TMS320TCI6488

NOT RECOMMENDED FOR NEW DESIGNS
Data sheet Order now

Product details

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  • Key Features
    • High-Performance Communications Infrastructure DSP (TCI6487/8)
    • Instruction Cycle Time: 1.25 ns to 0.83 ns (1.2-GHz Device); 1.25 ns to 1 ns (1-GHz Device)
    • Clock Rate: 800 MHz to 1.2 GHz (1.2-GHz Device); 800-MHz to 1-GHz (1-GHz Device)
    • Commercial Temperature and Extended Temperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • One Receive Accelerator (RAC) [TCI6488 Only]
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Communications Infrastructure DSP (TCI6487/8)
    • Instruction Cycle Time
      • 1.2-GHz Device: 1.25-ns to 0.83-ns(1)
      • 1-GHz Device: 1.25-ns to 1-ns
    • Clock Rate:
      • 1.2-GHz Device: 800-MHz to 1.2-GHz
      • 1-GHz Device: 800-MHz to 1-GHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature
      • 1.2-GHz Device 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
    • Extented Temperature
      • 1.2-GHz Device -40°C to 95°C
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 24 M-Bit (3072 K-Byte) Total L2 Unified Mapped RAM/Cache [Flexible Allocation]
      • Configurable at boot-time to 1 MB/1 MB/1 MB or 1.5 MB/1 MB/0.5 MB
    • 512 K-Bit (64 K-Byte) L3 ROM
  • One Receive Accelerator (RAC) [TCI6488 Only]
    • Performs Chip-Rate RX Functions
    • Up to 64 Macro-BTS Users
    • Up to 160 km cell size
  • Six RSAs for CDMA Processing (2 per core)
    • Dedicated RAKE, PATH_SEARCH and RACH_SEARCH Instructions
    • Transmit Processing Capability
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0: 614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Indepent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance information is presented in this document for the TCI6487 1.2-GHz device. The TCI6487/8 1.0-GHz DSP is a fully-qualified device.
All other trademarks are the property of their respective owners.

  • Key Features
    • High-Performance Communications Infrastructure DSP (TCI6487/8)
    • Instruction Cycle Time: 1.25 ns to 0.83 ns (1.2-GHz Device); 1.25 ns to 1 ns (1-GHz Device)
    • Clock Rate: 800 MHz to 1.2 GHz (1.2-GHz Device); 800-MHz to 1-GHz (1-GHz Device)
    • Commercial Temperature and Extended Temperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • One Receive Accelerator (RAC) [TCI6488 Only]
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Communications Infrastructure DSP (TCI6487/8)
    • Instruction Cycle Time
      • 1.2-GHz Device: 1.25-ns to 0.83-ns(1)
      • 1-GHz Device: 1.25-ns to 1-ns
    • Clock Rate:
      • 1.2-GHz Device: 800-MHz to 1.2-GHz
      • 1-GHz Device: 800-MHz to 1-GHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature
      • 1.2-GHz Device 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
    • Extented Temperature
      • 1.2-GHz Device -40°C to 95°C
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 24 M-Bit (3072 K-Byte) Total L2 Unified Mapped RAM/Cache [Flexible Allocation]
      • Configurable at boot-time to 1 MB/1 MB/1 MB or 1.5 MB/1 MB/0.5 MB
    • 512 K-Bit (64 K-Byte) L3 ROM
  • One Receive Accelerator (RAC) [TCI6488 Only]
    • Performs Chip-Rate RX Functions
    • Up to 64 Macro-BTS Users
    • Up to 160 km cell size
  • Six RSAs for CDMA Processing (2 per core)
    • Dedicated RAKE, PATH_SEARCH and RACH_SEARCH Instructions
    • Transmit Processing Capability
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0: 614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Indepent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance information is presented in this document for the TCI6487 1.2-GHz device. The TCI6487/8 1.0-GHz DSP is a fully-qualified device.
All other trademarks are the property of their respective owners.

The TMS320C64x+ DSPs (including the TMS320TCI6487/8 device) are the highest-performance communications infrastructure DSP generation in the TMS320C6000™ DSP platform.

The TCI6487/8 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI). It is designed specifically for wireless infrastructure baseband applications, providing an ideal platform for UMTS, TD-SCDMA, Wi-MAX and GSM/EDGE Macro, Micro, Pico, and Enterprise BTS; moreover, the device enables System-on-Chip (SoC) solutions in video and telecom infrastructure and medical imaging applications.

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The TMS320C64x+ DSPs (including the TMS320TCI6487/8 device) are the highest-performance communications infrastructure DSP generation in the TMS320C6000™ DSP platform.

The TCI6487/8 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI). It is designed specifically for wireless infrastructure baseband applications, providing an ideal platform for UMTS, TD-SCDMA, Wi-MAX and GSM/EDGE Macro, Micro, Pico, and Enterprise BTS; moreover, the device enables System-on-Chip (SoC) solutions in video and telecom infrastructure and medical imaging applications.

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.
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Technical documentation

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Type Title Date
* Data sheet TMS320TCI6487/8 Communications Infrastructure Digital Signal Processor datasheet (Rev. L) 11 Apr 2011
* Errata TMS320TCI6487/88 DSP Silicon Errata (Silicon Revs. 2.1, 2.0, 1.3, 1.2, 1.1, 1.0) (Rev. H) 11 Mar 2011
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
Application note Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 19 Jul 2013
User guide TMS320TCI6487/88 DSP EMAC/MDIO Module Reference Guide (Rev. C) 02 Mar 2012
Application note Tuning VCP2 and TCP2 Bit Error Rate Performance 11 Feb 2011
Application note TMS320TCI6487/88 Hardware Design Guide (Rev. E) 03 Aug 2010
Application note TMS320C6457/TMS320TCI6484/TMS320TCI6487/88 DDR2 Implementation Guidelines (Rev. D) 28 Jan 2010
User guide TMS320TCI648x DSP Viterbi-Decoder Coprocessor 2 (VCP2) User's Guide (Rev. E) 08 Dec 2009
Application note TMS320TCI648x Antenna Interface Programming 04 Nov 2009
Application note TMS320TCI6487/88 Power Consumption Summary (Rev. B) 24 Sep 2009
Application note TMS320TCI6488 Memory Access Performance 30 Jun 2009
User guide TMS320TCI6487/8 Chip Interrupt Controller (CIC) User's Guide 20 Aug 2008
User guide TMS320TCI6487/8 DSP Power/Sleep Controller (PSC) User's Guide (Rev. A) 15 Aug 2008
User guide TMS320TCI6487/8 Semaphore User's Guide (Rev. C) 06 Feb 2008
Application note TMS320TCI6488 SERDES Implementation Guidelines (Rev. A) 21 Aug 2007
User guide TMS320TCI6487/8 Frame Synchronization User's Guide (Rev. A) 05 Jul 2007
User guide TMS320TCI6487/8 Antenna Interface User's Guide (Rev. A) 26 Jun 2007
Application note TMS30TCI6488 RAC Internal Precisions 04 May 2007
More literature TMS320TCI6488 DSP Platform Product Bulletin 10 Jan 2007
Application note TMS320TCI TCP2 Channel Density 13 Dec 2006

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