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Product details

Parameters

Number of channels (#) 4 IO capacitance (Typ) (pF) 0.5 Vrwm (V) 5.5 IEC 61000-4-2 contact (+/- kV) 12 IEC 61000-4-5 (A) 2.5 Features Bi-/uni-directional Uni-Directional IO leakage current (Max) (nA) 1 Rating Catalog Operating temperature range (C) -40 to 125 Dynamic resistance (Typ) (Ω) 0.8 Clamping voltage (V) 10 open-in-new Find other ESD protection & TVS surge diodes

Package | Pins | Size

X2SON (DPW) 4 1 mm² .8 x .8 open-in-new Find other ESD protection & TVS surge diodes

Features

  • Provides System Level ESD Protection for Low-Voltage IO Interface
  • IO Capacitance 0.45pF (Typ)
  • IEC 61000-4-2 Level 4
    • ±12kV (Contact Discharge)
    • ±15kV (Air Gap Discharge)
  • IEC61000-4-5 (Surge): 2.5A (8/20 µs)
  • DC Breakdown Voltage 6.5V (Min)
  • Ultra Low Leakage Current 1nA (Max)
  • Low ESD Clamping Voltage
  • Industrial Temperature Range: –40°C to 125°C
  • Space Minimizing 0.8mm x 0.8mm DPW Package
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Description

The TPD4E110 is a uni-directional Electrostatic Discharge (ESD) protection device with ultra-low capacitance. The device is constructed with a central ESD clamp and features two hiding diodes per channel to reduce the capacitive loading. Each channel is rated to dissipate ESD strikes above the maximum level specified in the IEC61000-4-2 level 4 international standard. The TPD4E110's ultra-low loading capacitance makes the device ideal for protecting high-speed signal pins.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 10
Type Title Date
* Datasheet TPD4E110 4 Channel Protection Solution for Super-Speed (Up to 6 GBPS) Interface datasheet (Rev. B) Apr. 10, 2014
Application notes ESD Packaging and Layout Guide Aug. 27, 2020
User guides Generic ESD Evaluation Module User's Guide Apr. 03, 2018
Selection guides System-Level ESD Protection Guide (Rev. C) Feb. 20, 2018
Selection guides ESD by Interface Selection Guide (Rev. A) Jun. 26, 2017
User guides TPD4E110DPW Evaluation Module (Rev. A) Oct. 06, 2016
White papers Designing USB for short-to-battery tolerance in automotive environments Feb. 10, 2016
Application notes ESD Layout Guide Mar. 04, 2015
Application notes Design Considerations for System-Level ESD Circuit Protection Sep. 25, 2012
Application notes Reading and Understanding an ESD Protection Datasheet May 19, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
Texas Instrument's ESDEVM evaluation module allows the evaluation of most of TI's ESD portfolio. The board comes with all traditional ESD footprints in order to be able to test any number of devices. Devices that need to be tested can be soldered onto their respect footprint and then tested. For the (...)
Features
  • Allows testing of most TI ESD devices
  • Many footprints to allow testing of each part
  • S-parameter testing for signal integrity
EVALUATION BOARDS Download
document-generic User guide
49
Description

TPD4E110DPWEVM includes 15 TPD4E110DPW’s in various configurations for testing. Eight TPD4E110DPW’s are configured for IEC61000-4-2 compliance testing, two TPD4E110DPW are configured for 4-port S-parameter analysis, and four are configured for USB 3.0 Type A throughput analysis. The EVM (...)

Features
  • Space Saving 0.8mm x 0.8mm DPW package
  • System Level ESD Protection for Low-Voltage IO Interface
  • IEC 61000-4-2 Level 4 ESD protection
  • IO Capacitance: 0.45pF (Typ)
  • DC Breakdown Voltage: 6.5V (Min)

Design tools & simulation

SIMULATION MODELS Download
SLVMA71.ZIP (2 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
X2SON (DPW) 4 View options

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