Product details

Output options Adjustable Output Iout (Max) (A) 3 Vin (Max) (V) 5.5 Vin (Min) (V) 0.8 Vout (Max) (V) 3.6 Vout (Min) (V) 0.8 Noise (uVrms) 13 Iq (Typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Rating Catalog Load capacitance (Min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power Good, Soft Start Accuracy (%) 1 PSRR @ 100 KHz (dB) 50 Dropout voltage (Vdo) (Typ) (mV) 115 Operating temperature range (C) -40 to 125
Output options Adjustable Output Iout (Max) (A) 3 Vin (Max) (V) 5.5 Vin (Min) (V) 0.8 Vout (Max) (V) 3.6 Vout (Min) (V) 0.8 Noise (uVrms) 13 Iq (Typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Rating Catalog Load capacitance (Min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power Good, Soft Start Accuracy (%) 1 PSRR @ 100 KHz (dB) 50 Dropout voltage (Vdo) (Typ) (mV) 115 Operating temperature range (C) -40 to 125
TO-263 (KTW) 7 154 mm² 10.1 x 15.24 VQFN (RGR) 20 12 mm² 3.5 x 3.5 VQFN (RGW) 20 25 mm² 5 x 5 VQFN (RGW) 20 25 mm² 5.0 x 5.0
  • Input Voltage Range: 1.1 V to 5.5 V
  • Soft-Start (SS) Pin Provides a Linear Startup With Ramp Time Set by External Capacitor
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.9 V With External Bias Supply
  • Adjustable Output: 0.8 V to 3.6 V
  • Ultra-Low Dropout: 115 mV at 3.0 A (typical)
  • Stable With Any or No Output Capacitor
  • Excellent Transient Response
  • Open-Drain Power-Good (VQFN Only)
  • Packages: 5-mm × 5-mm × 1-mm VQFN (RGW), 3.5-mm × 3.5-mm VQFN (RGR), and DDPAK
  • Input Voltage Range: 1.1 V to 5.5 V
  • Soft-Start (SS) Pin Provides a Linear Startup With Ramp Time Set by External Capacitor
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.9 V With External Bias Supply
  • Adjustable Output: 0.8 V to 3.6 V
  • Ultra-Low Dropout: 115 mV at 3.0 A (typical)
  • Stable With Any or No Output Capacitor
  • Excellent Transient Response
  • Open-Drain Power-Good (VQFN Only)
  • Packages: 5-mm × 5-mm × 1-mm VQFN (RGW), 3.5-mm × 3.5-mm VQFN (RGR), and DDPAK

The TPS74401 low-dropout (LDO) linear regulators provide an easy-to-use robust power-management solution for a wide variety of applications. The user-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well-suited for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility lets the user configure a solution that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with specific start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The TPS74401 family of LDOs is stable without an output capacitor or with ceramic output capacitors. The device family is fully specified from TJ = –40°C to 125°C. The TPS74401 is offered in two 20-pin small VQFN packages (a 5-mm × 5-mm RGW and a
3.5-mm × 3.5-mm RGR package), yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK (KTW) package is also available.

The TPS74401 low-dropout (LDO) linear regulators provide an easy-to-use robust power-management solution for a wide variety of applications. The user-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well-suited for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility lets the user configure a solution that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with specific start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The TPS74401 family of LDOs is stable without an output capacitor or with ceramic output capacitors. The device family is fully specified from TJ = –40°C to 125°C. The TPS74401 is offered in two 20-pin small VQFN packages (a 5-mm × 5-mm RGW and a
3.5-mm × 3.5-mm RGR package), yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK (KTW) package is also available.

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Technical documentation

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Type Title Date
* Data sheet TPS74401 3.0-A, Ultra-LDO with Programmable Soft-Start datasheet (Rev. R) 06 Apr 2016
Application note LDO Noise Demystified (Rev. B) 18 Aug 2020
Application note Using Thermal Calculation Tools for Analog Components (Rev. A) 30 Aug 2019
Application note A Topical Index of TI LDO Application Notes (Rev. F) 27 Jun 2019
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 21 Mar 2018
Application note LDO PSRR Measurement Simplified (Rev. A) 09 Aug 2017
Application note 4Q 2012 Issue Analog Applications Journal 25 Sep 2012
Application note LDO noise examined in detail 25 Sep 2012
Application note Power Solution Using Discrete DC/DC Converters and LDOs (Rev. B) 26 Aug 2010
Application note Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A) 24 May 2010
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 28 Apr 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 26 Mar 2010
Application note Using New Thermal Metrics 15 Dec 2009
Application note A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W 10 Oct 2006
User guide TPS74x01EVM-118 User's Guide 20 Jun 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

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Limit: 3
Evaluation board

DAC38RF87EVM — DAC38RF87 Dual-Channel, 14-Bit, 6.2-GSPS, 6x-24x Interpolating, 6-GHz GSM PLL DAC Evaluation Module

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Limit: 3
Evaluation board

DAC38RF89EVM — DAC38RF89 Dual-Channel, 14-Bit, 8.4GSPS, 1x-24x Interpolating, 5 & 7.5 GHz PLL DAC Evaluation Module

The DAC38RF89 evaluation module (EVM) is the circuit board for evaluating DAC38RF89 digital-to-analog converters (DACs). The DAC38RFEVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC (...)

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Limit: 3
Evaluation board

TPS74401EVM-118 — TPS74401 Evaluation Module

The TPS74401EVM-118 evaluation module (EVM) is designed to help the user easily evaluate and test the operation and functionality of the TPS74401 LDO linear regulator. The EVM uses the TPS74401, 3 A linear regulator with programmable soft-start and integrated power good (PG). Refer to (...)

In stock
Limit: 5
Simulation model

TPS74401 Unencrypted PSpice Transient Model

SBVM619.ZIP (3 KB) - PSpice Model
Simulation model

TPS74401 PSpice Transient Model (Rev. B)

SLIM008B.ZIP (63 KB) - PSpice Model
Simulation model

TPS74401 TINA-TI Transient Reference Design

SLIM009.TSC (89 KB) - TINA-TI Reference Design
Simulation model

TPS74401 TINA-TI DC Reference Design

SLIM010.TSC (120 KB) - TINA-TI Reference Design
Simulation model

TPS74401 TINA-TI Transient Spice Model

SLIM011.ZIP (35 KB) - TINA-TI Spice Model
Schematic

PMP5149 1

SLVR354.PDF (150 KB)
Schematic

PMP5149 2

SLVR355.PDF (141 KB)
Schematic

PMP5149 3

SLVR356.PDF (193 KB)
Reference designs

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TIDA-01240 — RF-Sampling S-Band Radar Transmitter Reference Design

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Reference designs

TIDA-00270 — Current-Sharing Dual LDOs

This power supply topology is capable of sourcing 6A via two LDOs operating in parallel. The solution sources current evenly between the two TPS74401’s, each capable of supplying 3A. This design allows for higher currents to be supplied than is typically possible with a single LDO. It also (...)
Reference designs

TIDA-01084 — Continuous Wave Phase-aligned Multitone Generator: DC-to-6-GHz RF-Sampling DAC Reference Design

The TIDA-01084 reference design demonstrates the use of RF sampling DAC to generate continuous phase-aligned multitone waveforms. With four 48-bit independent NCOs, the 14-bit, 9GSPS DAC38RF83 can generate four CW tones placed anywhere within the first Nyquist zone or up to 6 GHz in the second.

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This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)
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TIDA-00309 — DisplayPort Video 4:1 Aggregation Reference Design

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TIDA-00069 — FPGA Firmware Example of How To Interface Altera FPGAs to High-Speed LVDS-Interface Data Converters

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Package Pins Download
DDPAK/TO-263 (KTW) 7 View options
VQFN (RGR) 20 View options
VQFN (RGW) 20 View options

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