Product details

Function USB2 USB speed (Mbps) 12 Supply voltage (V) 3.3 Rating Catalog Operating temperature range (C) -40 to 85
Function USB2 USB speed (Mbps) 12 Supply voltage (V) 3.3 Rating Catalog Operating temperature range (C) -40 to 85
LQFP (VF) 32 49 mm² 7 x 7
  • Fully Compliant With the USB Specification as a Full-Speed Hub: TID #30220231
  • 32-Pin LQFP (1) Package With a 0.8-mm Terminal Pitch or QFN Package With a 0.5-mm Pin Pitch
  • 3.3-V Low-Power ASIC Logic
  • Integrated USB Transceivers
  • State Machine Implementation Requires No Firmware Programming
  • One Upstream Port and Four Downstream Ports
  • All Downstream Ports Support Full-Speed and Low-Speed Operations
  • Two Power Source Modes
    • Self-Powered Mode
    • Bus-Powered Mode
  • Power Switching and Overcurrent Reporting Is Provided Ganged or Per Port
  • Supports Suspend and Resume Operations
  • Supports Programmable Vendor ID and Product ID With External Serial EEPROM
  • 3-State EEPROM Interface Allows EEPROM Sharing
  • Push-Pull Outputs for PWRON Eliminate the Need for External Pullup Resistors
  • Noise Filtering on OVRCUR Provides Immunity to Voltage Spikes
  • Package Pinout Allows 2-Layer PCB
  • Low EMI Emission Achieved by a 6-MHz Crystal Input
  • Migrated From Proven TUSB2040 Hub
  • Lower Cost Than the TUSB2040 Hub
  • Enhanced System ESD Performance
  • No Special Driver Requirements; Works Seamlessly With Any Operating System With USB Stack Support
  • Supports 6-MHz Operation Through a Crystal Input or a 48-MHz Input Clock

(1)JEDEC descriptor S-PQFP-G for low-profile quad flatpack (LQFP).

  • Fully Compliant With the USB Specification as a Full-Speed Hub: TID #30220231
  • 32-Pin LQFP (1) Package With a 0.8-mm Terminal Pitch or QFN Package With a 0.5-mm Pin Pitch
  • 3.3-V Low-Power ASIC Logic
  • Integrated USB Transceivers
  • State Machine Implementation Requires No Firmware Programming
  • One Upstream Port and Four Downstream Ports
  • All Downstream Ports Support Full-Speed and Low-Speed Operations
  • Two Power Source Modes
    • Self-Powered Mode
    • Bus-Powered Mode
  • Power Switching and Overcurrent Reporting Is Provided Ganged or Per Port
  • Supports Suspend and Resume Operations
  • Supports Programmable Vendor ID and Product ID With External Serial EEPROM
  • 3-State EEPROM Interface Allows EEPROM Sharing
  • Push-Pull Outputs for PWRON Eliminate the Need for External Pullup Resistors
  • Noise Filtering on OVRCUR Provides Immunity to Voltage Spikes
  • Package Pinout Allows 2-Layer PCB
  • Low EMI Emission Achieved by a 6-MHz Crystal Input
  • Migrated From Proven TUSB2040 Hub
  • Lower Cost Than the TUSB2040 Hub
  • Enhanced System ESD Performance
  • No Special Driver Requirements; Works Seamlessly With Any Operating System With USB Stack Support
  • Supports 6-MHz Operation Through a Crystal Input or a 48-MHz Input Clock

(1)JEDEC descriptor S-PQFP-G for low-profile quad flatpack (LQFP).

The TUSB2046x is a 3.3-V CMOS hub device that provides one upstream port and four downstream ports in compliance with the Universal Serial Bus (USB) specification as a full-speed hub. Because this device is implemented with a digital state machine instead of a microcontroller, no firmware
programming is required. Fully compliant USB transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support full-speed and low-speed devices by automatically setting the slew rate according to the speed of the device attached to the ports. The configuration of the BUSPWR pin selects either the bus-powered or the self-powered mode.

Configuring the GANGED input determines the power switching and overcurrent detection modes for the downstream ports. If GANGED is high, all PWRON outputs switch together and if any OVRCUR is activated, all ports transition to the power-off state. If GANGED is low, the PWRON outputs and OVRCUR inputs operate on a per-port basis.

The TUSB2046x provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the device. When TSTMODE is high, the TSTPLL/48MCLK input is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered down while TSTMODE is high. Low EMI emission is achieved because the TUSB2046x can usee a 6-MHz crystal input. Connect the crystal as shown in Figure 6. An internal PLL then generates the 48-MHz clock used to sample data from the upstream port and to synchronize the 12 MHz used for the USB clock. If low-power suspend and resume are desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting the output to the XTAL1 pin and leaving the XTAL2 pin open. The oscillator TTL output must not exceed 3.6 V.

For 48-MHz operation, the clock cannot be generated with a crystal using the XTAL2 output because the internal oscillator cell supports only the fundamental frequency. Other useful features of the TUSB2046x include a package with a 0.8-mm pin pitch for easy PCB routing and assembly, push-pull outputs for the PWRON pins eliminate the need for pullup resistors required by traditional open-collector I/Os, and OVRCUR pins have noise filtering for increased immunity to voltage spikes.

The TUSB2046x is a 3.3-V CMOS hub device that provides one upstream port and four downstream ports in compliance with the Universal Serial Bus (USB) specification as a full-speed hub. Because this device is implemented with a digital state machine instead of a microcontroller, no firmware
programming is required. Fully compliant USB transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support full-speed and low-speed devices by automatically setting the slew rate according to the speed of the device attached to the ports. The configuration of the BUSPWR pin selects either the bus-powered or the self-powered mode.

Configuring the GANGED input determines the power switching and overcurrent detection modes for the downstream ports. If GANGED is high, all PWRON outputs switch together and if any OVRCUR is activated, all ports transition to the power-off state. If GANGED is low, the PWRON outputs and OVRCUR inputs operate on a per-port basis.

The TUSB2046x provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the device. When TSTMODE is high, the TSTPLL/48MCLK input is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered down while TSTMODE is high. Low EMI emission is achieved because the TUSB2046x can usee a 6-MHz crystal input. Connect the crystal as shown in Figure 6. An internal PLL then generates the 48-MHz clock used to sample data from the upstream port and to synchronize the 12 MHz used for the USB clock. If low-power suspend and resume are desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting the output to the XTAL1 pin and leaving the XTAL2 pin open. The oscillator TTL output must not exceed 3.6 V.

For 48-MHz operation, the clock cannot be generated with a crystal using the XTAL2 output because the internal oscillator cell supports only the fundamental frequency. Other useful features of the TUSB2046x include a package with a 0.8-mm pin pitch for easy PCB routing and assembly, push-pull outputs for the PWRON pins eliminate the need for pullup resistors required by traditional open-collector I/Os, and OVRCUR pins have noise filtering for increased immunity to voltage spikes.

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* Data sheet TUSB2046x 4-Port Hub for the Universal Serial Bus With Optional Serial EEPROM Interface datasheet (Rev. L) PDF | HTML 28 Jun 2017

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