Automotive 3-A, 120-V half bridge driver with 5-V UVLO, interlock and enable
Product details
Parameters
Package | Pins | Size
Features
- AEC-Q100 qualified with following results
- Temperature grade 1 (Tj = –40°C to 150°C)
- HBM ESD classification level 1B
- CDM ESD classification level C3
- Drives two N-channel MOSFETs in high-side low-side configuration
- 5-V typical under voltage lockout
- Input interlock
- Enable/disable functionality in DRC package
- 16-ns typical propagation delay
- 12-ns rise, 10-ns fall time with 1.8-nF load
- 1-ns typical delay matching
- Absolute Maximum Negative Voltage Handling on Inputs (–5 V)
- Absolute Maximum Negative Voltage Handling on HS (–14 V)
- 3.5-A sink, 2.5-A Source output currents
- Absolute maximum boot voltage 120 V
- Low current (7-µA) consumption when disabled
- Integrated bootstrap diode
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Description
The UCC27282-Q1 is a robust N-channel MOSFET driver with a maximum switch node (HS) voltage rating of 100 V. It allows for two N-channel MOSFETs to be controlled in half-bridge or synchronous buck configuration based topologies. Its 3.5-A peak sink current and 2.5-A peak source current along with low pull-up and pull-down resistance allows the UCC27282-Q1 to drive large power MOSFETs with minimum switching losses during the transition of the MOSFET Miller plateau. Since the inputs are independent of the supply voltage, UCC27282-Q1 can be used in conjunction with both analog and digital controllers.
The input pins as well as the HS pin are able to tolerate significant negative voltage, which improves system robustness. Input interlock further improves robustness and system reliability in high noise applications. The enable and disable functionality provides additional system flexibility by reducing power consumption by the driver and responds to fault events within the system. 5-V UVLO allows systems to operate at lower bias voltages, which is necessary in many high frequency applications and improves system efficiency in certain operating modes. Small propagation delay and delay matching specifications minimize the dead-time requirement which further improves efficiency.
Under voltage lockout (UVLO) is provided for both the high-side and low-side driver stages forcing the outputs low if the VDD voltage is below the specified threshold. An integrated bootstrap diode eliminates the need for an external discrete diode in many applications, which saves board space and reduces system cost. UCC27282-Q1 is offered in a small package enabling high density designs.
Same functionality and pinout but is not an equivalent to the compared device:
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | UCC27282-Q1 Automotive 120-V Half-Bridge Driver with Cross Conduction Protection and Low Switching Losses datasheet (Rev. A) | Jun. 23, 2020 |
Application note | Understanding and comparing peak current capability of gate drivers | Mar. 30, 2021 | |
More literature | Best practices for half-bridge gate drivers for HEV/EV | Mar. 23, 2021 | |
User guide | UCC27282 Evaluation Module (Rev. A) | Jan. 06, 2020 | |
Application note | UCC27282 Improving motor drive system robustness | Jan. 11, 2019 | |
Technical article | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | Sep. 19, 2018 | |
Technical article | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | May 30, 2018 | |
Technical article | Boosting efficiency for your solar inverter designs | May 24, 2018 | |
Technical article | How to achieve higher system robustness in DC drives, part 1: negative voltage | Apr. 17, 2018 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- High performance driver with input and output interface
- Ability to test most data sheet parameters
- Ability to compare performance of various drivers with compatible pinout
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
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CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 8 | View options |
VSON (DRC) | 10 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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